PRELIMINARY DATA SHEET
µ
PD45256441, 45256841, 45256163
256M-bit Synchronous DRAM
4-bank, LVTTL
MOS INTEGRATED CIRCUIT
Description
The
µ
PD45256441, 45256841, 45256163 are high-speed 268,435,456 bit synchronous dynamic random-access
memories, organized as 16,777,216x4x4, 8,388,608x8x4, 4,194,304x16x4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1(Bank Select)
Byte control (x16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
x4, x8, x16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
8,192 refresh cycles/64 ms
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13394EJ3V0DS00 (3rd edition)
Date Published April 1999 NS CP (K)
Printed in Japan
The mark
5
shows major revised points.
©
1998
µ
PD45256441, 45256841, 45256163
Pin Configurations
/xxx indicates active low signal.
[
µ
PD45256441]
54-pin Plastic TSOP(II) (400mil)
16M word x 4 bit x 4 bank
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SS
Q
NC
DQ3
V
CC
Q
NC
NC
V
SS
Q
NC
DQ2
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
A0 to A12
BA0, BA1
Note
: Address inputs
: Bank select
: Data inputs/outputs
: Clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
DQ0 to DQ3
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Note
A0 to A12
: Row address inputs
A0 to A9, A11 : Column address inputs
4
Preliminary Data Sheet M13394EJ3V0DS00
µ
PD45256441, 45256841, 45256163
[
µ
PD45256841]
54-pin Plastic TSOP(II) (400mil)
8M word x 8 bit x 4 bank
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
A0 to A12
BA0, BA1
Note
: Address inputs
: Bank select
: Data inputs/outputs
DQ0 to DQ7
CLK
CKE
/CS
: Clock input
: Clock enable
: Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE
V
CC
V
SS
: Write enable
: Supply voltage
: Ground
DQM : DQ mask enable
V
CC
Q : Supply voltage for DQ
V
SS
Q : Ground for DQ
NC
: No connection
Note
A0 to A12 : Row address inputs
A0 to A9 : Column address inputs
Preliminary Data Sheet M13394EJ3V0DS00
5
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