54AC164245
Rad-hard 16-bit transceiver 3.3 V to 5 V bidirectional level shifter
Datasheet
-
production data
•
Fail safe
•
Cold spare
•
Hermetic package
•
100 krad (Si) at any Mil1019 dose rate
•
SEL immune to 110MeV.cm
2
/mg LET ions
•
RHA QML-V qualified
Description
Ceramic Flat-48
The upper metallic lid is not electrically connected to
any pins, nor to the IC die inside the package
The 54AC164245 is a rad-hard advanced high-
speed CMOS, Schmitt trigger 16-bit bidirectional
multi-purpose transceiver with 3-state outputs and
cold sparing.
Designed for use as an interface between a 5 V
bus and a 3.3 V bus in mixed 5 V/3.3 V supply
systems, it achieves high-speed operation while
maintaining the CMOS low-power dissipation.
All pins have cold spare buffers to change them to
high impedance when V
DD
is tied to ground.
This IC is intended for two-way asynchronous
communication between the data buses. The
direction of the data transmission is determined
by the nDIR inputs.
The A port interfaces with the 3.3 V bus but can
also operate at 2.3 V. The B port operates with the
5 V bus.
Features
•
Fully compatible with 54ACS164245
•
Dual supply bidirectional level shifter
•
Extended voltage range from 2.3 V to 5.5 V
•
Separated enable pin for 3-state output
•
Schmidt-triggered I/Os: 100 mV hysteresis
•
Internal 26
Ω
limiting resistor on each I/O
•
High speed: Tpd = 8 ns maximum
Table 1. Device summary
Order codes
RHFAC164245K1
SMD pin
-
Quality level Package Lead finish Mass
Engineering
model
EPPL Temp. range
-
Yes
-55 °C to
125 °C
Flat-48
Gold
1.50 g
RHRAC164245K01V 5962R9858008VYC QML-V flight
April 2014
This is information on a product in full production.
DocID18093 Rev 4
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Contents
54AC164245
Contents
1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
Cold spare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
4
5
6
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Radiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
Ceramic Flat-48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Other information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
8.2
Data code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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54AC164245
Functional description
1
Functional description
Figure 1. Logic diagram
Table 2. Function table
Enable, OEx
L
H
Direction, DIRx
L
H
X
Operation
B data to A bus
A data to B bus
Isolation
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Functional description
54AC164245
1.1
Cold spare
The 54AC164245 features a cold spare input and output buffer. In high reliability
applications, cold sparing enables a redundant device to be tied to the data bus with its
power supply at 0 V (V
DD
= V
SS
, V
DD
- V
SS
= 0 V) without affecting the bus signals or
injecting current from the I/Os to the power supplies. Cold sparing also allows redundant
devices to be kept unpowered so that they can be switched on only when required. Power
consumption is therefore reduced by switching off the redundant circuit. This has no impact
on the application. Cold sparing is achieved by implementing a high impedance between
I/Os and V
DD
. The ESD protection is ensured through a non-conventional dedicated
structure.
1.2
Power-up
During power-up, all outputs are forced to high impedance. The high-impedance state is
maintained approximately until V
DD
is high, thus avoiding any transient and erroneous
signals during power-up.
1.3
Pin connections
Figure 2. Pin connections
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54AC164245
Table 3. Pin descriptions
Pin number
1
2, 3, 5, 6, 8, 9, 11, 12
4,10, 15, 21, 28, 34, 39, 45
7, 18
13, 14, 16, 17, 19, 20, 22, 23
24
25
31, 42
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
48
Symbol
DIR1
1B1 to 1B8
V
SS
V
DD1
2B1 to 2B8
DIR2
nG2
V
DD2
1A1 to 1A8
2A1 to 2A8
nG1
Functional description
Name and function
Direction control inputs
Side B inputs or 3-state outputs (5 V port)
Reference voltage to ground
Supply voltage (5 V)
Side B inputs or 3-state outputs (5 V port)
Direction control inputs
Output enable inputs (active low)
Supply voltage (3.3 V)
Side A inputs or 3-state outputs (3.3 V port)
Side A inputs or 3-state outputs (3.3 V port)
Output enable inputs (active low)
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测试/测量
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