TSPC603p
PowerPC 603e™ RISC MICROPROCESSOR Family
PID7v-603e Specification
DESCRIPTION
The PID7v-603e implementation of PowerPC603e (after
named 603p) is a low-power implementation of reduced
instruction set computer (RISC) microprocessors PowerPC™
family. The 603p implements 32-bit effective addresses, inte-
ger data types of 8, 16 and 32 bits, and floating-point data types
of 32 and 64 bits.
The 603p is a low-power 2.5/3.3-volt design and provides four
software controllable power-saving modes.
The 603p is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603p makes completion appear sequential. The 603p inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603p provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603p has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603p interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603p supports single-beat and burst data
transfers for memory accesses, and supports memory-
mapped I/O.
The 603p uses an advanced, 2.5/3.3-V CMOS process tech-
nology and maintains full interface compatibility with TTL devi-
ces.
The 603p integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
CERQUAD 240
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
MAIN FEATURES
H
4.0 SPECint95, 5.3 SPECfp95 @ 166 MHz (estimated)
H
Superscalar (3 instructions per clock peak).
H
Dual 16KB caches.
H
Selectable bus clock.
H
32-bit compatibility PowerPC implementation.
H
On chip debug support.
H
P
D
typical = 3.0 Watts (166 MHz), full operating conditions.
H
Nap, doze and sleep modes for power savings.
H
Branch folding.
H
64-bit data bus (32-bit data bus option).
H
4-Gbyte direct addressing range.
H
Pipelined single/double precision float unit.
H
H
H
H
IEEE 754 compatible FPU.
IEEE P 1149-1 test mode (JTAG/C0P).
f
int
max = 166 MHz. (200 MHz planned).
f
bus
max = 66.67 MHz.
Compatible CMOS input / TTL Output.
G suffix
CBGA 255
Ceramic Ball Grid Array
(To be introduced)
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H
MIL-STD-883 class B or According to TCS standards
(planned)
H
Upscreenings based upon TCS standards
H
Full military temperature range (T
c
= -55°C, Tc= +125°C)
Industrial temperature range (T
c
=
–
40°C, T
c
= +110°C)
H
Internal // I/O Power Supply = 2.5
±
5 % // 3.3 V
±
5 %.
H
240 pin Cerquad or 255 pin CBGA packages
June 1998
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TSPC603p
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3
1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. CQFP 240 package . . . . . . . . . . . . . . . . . . . . . 4
2.2. CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3. Pinout listing . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 8
5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 24
5.1. PowerPC registers and programming
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1.
5.1.2.
5.1.3.
5.1.4.
5.1.5.
5.1.6.
5.1.7.
General-Purpose Registers (GPRs) . . 24
Floating-Point Registers (FPRs) . . . . . 24
Condition Register (CR) . . . . . . . . . . . . 24
Floating-Point Status and Control Register
(FPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Machine State Register (MSR) . . . . . . 24
Segment Registers (SRs) . . . . . . . . . . . 24
Special-Purpose Registers (SPRs) . . . 24
B. DETAILED SPECIFICATIONS . . . . . . . . . . 11
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . 11
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2. Design and construction . . . . . . . . . . . . . . . . 11
3.2.1.
3.2.2.
3.2.3.
Terminal connections . . . . . . . . . . . . . . . 11
Lead material and finish . . . . . . . . . . . . 11
Package . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2. Instruction set and addressing modes . . . . 27
5.2.1.
5.2.2.
PowerPC instruction set and addressing
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerPC 603p microprocessor instruction
set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3. Cache implementation . . . . . . . . . . . . . . . . . . 28
5.3.1.
5.3.2.
PowerPC cache characteristics . . . . . . 28
PowerPC 603p microprocessor cache
implementation . . . . . . . . . . . . . . . . . . . . 28
5.4. Exception model . . . . . . . . . . . . . . . . . . . . . . . 29
5.4.1.
5.4.2.
PowerPC exception model . . . . . . . . . . 29
PowerPC 603p microprocessor exception
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3. Absolute maximum ratings . . . . . . . . . . . . . . 11
3.4. Thermal characteristics . . . . . . . . . . . . . . . . . 12
3.4.1.
3.4.2.
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
CQFP240 package . . . . . . . . . . . . . . . . 12
CBGA255 package . . . . . . . . . . . . . . . . 13
Dynamic Power Management . . . . . . .
Programmable Power Modes . . . . . . . .
Power Management Modes . . . . . . . . .
Power Management Software
Considerations . . . . . . . . . . . . . . . . . . . .
Power dissipation . . . . . . . . . . . . . . . . . .
14
14
14
16
16
5.5.1.
5.5.2.
5.5. Memory management . . . . . . . . . . . . . . . . . . 33
PowerPC memory management . . . . . 33
PowerPC 603p microprocessor memory
management . . . . . . . . . . . . . . . . . . . . . . 33
3.5. Power consideration . . . . . . . . . . . . . . . . . . . 14
5.6. Instruction timing . . . . . . . . . . . . . . . . . . . . . . 33
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 34
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2. Certificate of compliance . . . . . . . . . . . . . . . . 34
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . 35
8.1. 240 pins - CQFP . . . . . . . . . . . . . . . . . . . . . . . 35
8.2. BGA package description . . . . . . . . . . . . . . . 36
8.2.1.
8.2.2.
Package parameters . . . . . . . . . . . . . . . 36
Mechanical dimensions of the BGA pack-
age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . 17
4.1. General requirements . . . . . . . . . . . . . . . . . . 17
4.2. Static characteristics . . . . . . . . . . . . . . . . . . . 17
4.3. Dynamic characteristics . . . . . . . . . . . . . . . . 18
4.3.1.
4.3.2.
4.3.3.
Clock AC specifications . . . . . . . . . . . . . 18
Input AC specifications . . . . . . . . . . . . . 19
Output AC specifications . . . . . . . . . . . . 20
9. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . 37
10. ORDERING INFORMATION . . . . . . . . . . . . . . . . 38
4.4. JTAG AC timing specifications . . . . . . . . . . . 22
2/38
TSPC603p
A. GENERAL DESCRIPTION
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b
address
64b
data
System Bus
Figure 1 : Block diagram
1. INTRODUCTION
The 603p is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micro-
processors. The 603p implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer
data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC
architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603p provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in
nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management
mode that causes the functional units in the 603p to automatically enter a low-power mode when the functional units are idle without
affecting operational performance, software execution, or any external hardware.
The 603p is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute
out of order for increased performance ; however, the 603p makes completion appear sequential.
The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store
unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for 603p-based systems. Most integer instructions execute in one clock
cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603p provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data
and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data
and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address
translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The
603p also supports block address translation through the use of two independent instruction and data block address translation (IBAT
and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during
block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT
translation takes priority.
The 603p has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603p interface protocol allows multiple masters to
compete for system resources through a central external arbiter. The 603p provides a three-state coherency protocol that supports
the exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/in-
valid) four-state protocol and operates coherently in systems that contain four-state caches. The 603p supports single-beat and burst
data transfers for memory accesses, and supports memory-mapped I/O.
The 603p uses an advanced, 0.35
mm
5 metal layer CMOS process technology and maintains full interface compatibility with TTL
devices.
3/38
TSPC603p
2. PIN ASSIGNMENTS
2.1. CQFP 240 package
Figure 2 : CQFP 240 : Top view
4/38
TSPC603p
2.2. CBGA255 package
Figure 3 (pin matrix) shows the pinout as viewed from the top of the CBGA package. The direction of the top surface view is shown by
the side profile of the CBGA package.
Pin matrix top view
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Not to scale
Substrate Assembly
Die
VIEW
Encapsulant
Figure 3 : CBGA 255 Top view
5/38
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