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TS83C51RD2-LCMB

产品描述Microcontroller, 8-Bit, MROM, 8051 CPU, 40MHz, CMOS, PQFP64,
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小447KB,共74页
制造商Atmel (Microchip)
下载文档 详细参数 全文预览 文档解析

TS83C51RD2-LCMB概述

Microcontroller, 8-Bit, MROM, 8051 CPU, 40MHz, CMOS, PQFP64,

TS83C51RD2-LCMB规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Atmel (Microchip)
零件包装代码QFP
包装说明QFP, QFP64,.47SQ,20
针数64
Reach Compliance Codecompliant
位大小8
CPU系列8051
JESD-30 代码S-PQFP-G64
JESD-609代码e0
湿度敏感等级1
端子数量64
最高工作温度70 °C
最低工作温度
封装主体材料PLASTIC/EPOXY
封装代码QFP
封装等效代码QFP64,.47SQ,20
封装形状SQUARE
封装形式FLATPACK
电源3/5 V
认证状态Not Qualified
RAM(字节)1024
ROM(单词)65536
ROM可编程性MROM
速度40 MHz
最大压摆率13 mA
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.5 mm
端子位置QUAD

文档解析

TS80C51RA2 是一款基于 80C51 架构的高性能 CMOS 8 位微控制器,提供 ROMless 版本,无内部程序存储器,需外部扩展。核心特性包括兼容 80C51 引脚和指令集,最高操作频率达 40MHz(5V 下),支持 X2 速度提升机制,可将机器周期缩短至 6 个时钟周期,等效性能提升至 60MHz。内存配置包含 256 字节内部 RAM 和 256 字节扩展 RAM(XRAM),总计 512 字节数据存储空间,以及四个 8 位 I/O 端口和三个 16 位定时器/计数器。 增强功能包括可编程计数器阵列(PCA),支持高速输出、比较/捕获和脉宽调制模式;硬件看门狗定时器提升系统可靠性;增强型 UART 支持全双工通信、帧错误检测和自动地址识别,适用于多处理器环境。中断系统提供 7 个中断源和 4 级优先级管理,确保灵活的事件处理。完全静态设计允许时钟频率降至 DC 而不丢失数据。 电源管理支持空闲模式和掉电模式,有效降低功耗,工作电压范围 4.5-5V 或 2.7-5.5V。温度范围覆盖商用(0-70°C)和工业(-40-85°C)环境。封装选项包括 PDIL40、PLCC44 和 VQFP44 等,满足多样化的应用集成需求。

TS83C51RD2-LCMB文档预览

TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
High Performance 8-bit Microcontrollers
1. Description
Atmel Wireless & Microcontrollers TS80C51Rx2 is high
performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit
microcontroller.
The TS80C51Rx2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16/32/64 Kbytes), 256
bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable
Counter Array, an XRAM of 256 or 768 bytes, a
Hardware Watchdog Timer, a more versatile serial
channel that facilitates multiprocessor communication
(EUART) and a X2 speed improvement mechanism.
The fully static design of the TS80C51Rx2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51Rx2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
2 extra 8-bit I/O ports available on RD2 with high
pin count packages
Asynchronous port reset
Interrupt Structure with
7 Interrupt sources,
4 level priority interrupt system
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
Low EMI (inhibit ALE)
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-
bytes)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
Once mode (On-chip Emulation)
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Programmable Counter Array with
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window), PLCC68, VQFP64
1.4, JLCC68 (window)
Rev. C - 06 March, 2001
1
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
PDIL40
PLCC44
VQFP44 1.4
TS80C51RA2
TS80C51RD2
TS83C51RB2
TS83C51RC2
TS83C51RD2
TS87C51RB2
TS87C51RC2
TS87C51RD2
0
0
16k
32k
64k
0
0
0
0
0
0
0
0
16k
32k
64k
256
768
256
256
768
256
256
768
512
1024
512
512
1024
512
512
1024
32
32
32
32
32
32
32
32
ROM (bytes)
EPROM (bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
I/O
PLCC68
ROM (bytes)
VQFP64 1.4
TS80C51RD2
TS83C51RD2
TS87C51RD2
0
64k
0
0
0
64k
768
768
768
EPROM (bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
1024
1024
1024
I/O
48
48
48
3. Block Diagram
T2EX
P5
RxD
TxD
Vcc
Vss
PCA
ECI
T2
(1)
Watch
Dog
(3) (3)
XTAL1
XTAL2
ALE/ PROG
PSEN
CPU
EA/V
PP
RD
WR
(3)
(3)
Timer 0
Timer 1
INT
Ctrl
EUART
RAM
256x8
(1)
(1) (1)
ROM
/EPROM
0/16/32/64Kx8
XRAM
256/768x8
PCA
Timer2
C51
CORE
IB-bus
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5
(2)
(2)
(3) (3)
RESET
T0
T1
(3) (3)
P1
P2
P3
INT0
INT1
P0
P4
(1): Alternate function of Port 1
(2): Only available on high pin count packages
(3): Alternate function of Port 3
2
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P0, P1, P2, P3, P4, P5
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
Power and clock control registers: PCON
HDW Watchdog Timer Reset: WDTRST, WDTPRG
PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi
Interrupt system registers: IE, IP, IPH
Others: AUXR, CKCON
Table 1. All SFRs with their address and their reset value
Bit
addressable
0/8
1/9
CH
0000 0000
B
0000 0000
P5 bit
addressable
1111 1111
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
P4 bit
addressable
1111 1111
IP
X000 000
P3
1111 1111
IE
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
4/C
5/D
6/E
TH0
0000 0000
TH1
0000 0000
AUXR
XXXXXX00
CKCON
XXXX XXX0
PCON
00X1 0000
7/F
SBUF
XXXX XXXX
SADDR
0000 0000
AUXR1
XXXX0XX0
WDTRST
XXXX XXXX
WDTPRG
XXXX X000
SADEN
0000 0000
IPH
X000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
P5 byte
addressable
1111 1111
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
CL
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAPL2L
XXXX XXXX
CCAPL3L
XXXX XXXX
CCAPL4L
XXXX XXXX
2/A
CCAP0H
XXXX XXXX
3/B
CCAP1H
XXXX XXXX
Non Bit addressable
4/C
CCAPL2H
XXXX XXXX
5/D
CCAPL3H
XXXX XXXX
6/E
CCAPL4H
XXXX XXXX
7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
reserved
Rev. C - 06 March, 2001
3
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
5. Pin Configuration
P1.0 / T2
P1.1 / T2EX
P1.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 / A0
VSS1/NIC*
P1.1/T2EX
P0.2/AD2
P0.3/AD3
39
38
37
36
35
34
33
32
31
30
29
P0.0/AD0
P0.1/AD1
P0.1 / A1
P0.2 / A2
P1.4
P1.3
P1.2
P0.3 / A3
P0.4 / A4
P0.5 / A5
P0.6 / A6
P0.7 / A7
EA/VPP
ALE/PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44 43 42 41 40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.3
P1.4
P1.0/T2
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
PDIL/
CDIL40
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
PLCC/CQPJ 44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
NIC*
P2.0/A8
XTAL2
XTAL1
P2.2/A10
P2.3/A11
P2.4/A12
P3.7/RD
P2.1/A9
VSS
VSS1/NIC*
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43
42 41 40
39
38 37 36 35 34
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
VQFP44 1.4
12 13 14 15 16 17 18 19 20 21 22
XTAL1
NIC*
P2.0/A8
XTAL2
P2.3/A11
P2.4/A12
P2.1/A9
VSS
P2.2/A10
P3.6/WR
P3.7/RD
*NIC: No Internal Connection
4
P0.3/AD3
P1.0/T2
VCC
P1.4
P1.3
P1.2
VCC
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA/VPP
NIC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ALE/PROG
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
P4.0
P1.1/T2EX
P1.2
P1.3
P4.1
P1.4
P4.2
60
59
58
57
56
55
54
53
PLCC 68
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
P1.5
P1.6
P1.7
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P4.4
P3.6/WR
P4.3
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
VSS
P1.0/T2
P4.0
P1.1/T2EX
P1.2
P1.3
P4.1
P1.4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
VQFP64 1.4
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P4.4
P3.6/WR
P4.3
NIC: No InternalConnection
Rev. C - 06 March, 2001
P4.2
P1.5
P1.6
P1.7
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
5

 
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