Data Sheet
April 20, 2004
LCK4310
Low-Voltage PLL Clock Driver
1 Features
s
s
s
s
s
s
s
s
Output operating frequencies up to 1.25 GHz max.
100 ps part–to–part skew.
40 ps typical output–to–output skew.
Cycle-to-cycle jitter 5 ps max.
3.3 V and 2.5 V compatible.
Internal input pulldown resistors.
Q output will default low with inputs open or at V
EE
.
Meets or exceeds Joint Electron Device Engineering
Council (JEDEC) specification
EIA
®
/JESD78 IC latchup
test.
Moisture sensitivity level 1.
Flammability rating:
UL
®
–94 code V–0 at 1/8 in., oxygen
index 28 to 34.
Pin-for-pin compatible with
ON Semiconductor
®
part
number MC100LVE310.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
Ω,
even if only one side is being used. In
most applications, all eight differential pairs will be used
and therefore terminated. In the case where fewer than
eight pairs are used and in order to maintain minimum
skew, it is necessary to terminate at least the output pairs
adjacent to the output pair being used. Failure to follow this
guideline will result in small degradations of propagation
delay (on the order of 10 ps—20 ps) of the outputs being
used. While not catastrophic to most designs, this will result
in an increase in skew.
Note:
The package corners isolate outputs from one anoth-
er such that the guideline expressed above holds only
for outputs on the same side of the package.
The LCK4310, as with most ECL devices, can be operated
from a positive voltage supply (V
DD
) in LVPECL mode. This
allows the LCK4310 to be used for high-performance clock
distribution in 3.3 V/2.5 V systems. Designers can take
advantage of the LCK4310’s performance to distribute low-
skew clocks across the backplane or the board. In a PECL
environment (series or Thevenin), line terminations are
typically used since they require no additional power
supplies. If parallel termination is desired, a terminating
voltage of V
DD –
2.0 V will need to be provided.
An internally generated voltage supply (V
BB
pin) is
available to this device only. For single-ended input
conditions, the unused differential input is connected to
V
BB
as a switching reference voltage. V
BB
may also rebias
ac coupled inputs. When used, decouple V
BB
and V
DD
via a
0.01 µF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open.
s
s
s
2 Description
The LCK4310 is a low-voltage, low-skew 2:8 differential
emitter-coupled logic (ECL) fanout buffer designed with
clock distribution in mind. The device features fully
differential clock paths to minimize both device and system
skew. The LCK4310 offers two selectable clock inputs to
allow for redundant or test clocks to be incorporated into
the system clock trees.
LCK4310
Low-Voltage PLL Clock Driver
Data Sheet
April 20, 2004
3 Pin Information
3.1 Pin Diagram
V
DDO
Q0
Q1
Q1
Q2
20
25
Q0
24
23
22
V
EE
CLK_SEL
26
27
19
21
Q2
18
17
16
15
14
13
12
Q3
Q3
Q4
V
DDO
Q4
Q5
Q5
CLKa
28
V
DD
CLKa
V
BB
CLKb
1
2
3
4
CLKb
NC
Figure 3-1. 28-Pin PLCC
WARNING: All V
DD
, V
DDO
, and V
EE
pins must be externally connected to a power supply to guarantee proper oper-
ation.
2
V
DDO
Q6
10
Q7
Q6
11
6
7
8
5
Q7
9
Agere Systems Inc.
Data Sheet
April 20, 2004
3.2 Pin Descriptions
Table 3-1. Pin Descriptions
Pin
1
2
3
4
5
6
7, 10, 12, 14, 17, 19, 21, 24
8, 15, 22
9, 11, 13, 16, 18, 20, 23, 25
26
27
Symbol
V
DD
CLKa
V
BB
CLKb
CLKb
NC
Q[7:0]
V
DDO
Q[7:0]
V
EE
CLK_SEL
Type
Power
PECL
V
REFOUT
PECL
PECL
—
PECL
Power
PECL
Power
LVTTL
I/O
I
O
I
I
O
O
I
LCK4310
Low-Voltage PLL Clock Driver
Description
ECL Differential Input Clock.
Makes input pair with CLKa.
Reference Voltage Output.
ECL Differential Input Clock.
Makes input pair with CLKb.
ECL Differential Input Clock.
Makes input pair with CLKb.
ECL Differential Outputs.
ECL Differential Outputs.
ECL Input Clock Select.
0 = CLKa selected.
1 = CLKb selected.
ECL Differential Input Clock.
Makes input pair with CLKa.
—
Positive Power Supply.
—
No Connect.
—
Positive Power Supply.
—
Negative Power Supply.
28
CLKa
PECL
I
3.3 Logic Symbol
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
V
BB
CLKa
CLKa
CLKb
CLKb
CLK_SEL
CLK_SEL
L
H
Input Clock
CLKa/CLKa Selected
CLKb/CLKb Selected
Figure 3-2. Logic Symbol
Agere Systems Inc.
3
LCK4310
Low-Voltage PLL Clock Driver
Data Sheet
April 20, 2004
4 Absolute Maximum Ratings
Stresses which exceed the absolute maximum ratings can cause permanent damage to the device. These are absolute
stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods of time can
adversely affect device reliability.
Table 4-1. Absolute Maximum Ratings
Parameter
PECL Mode Positive Power Supply
Input Voltage:
PECL Mode Positive Input Voltage
Output Current
V
BB
Sink/Source
Storage Temperature Range
Wave Solder
Symbol
V
DD
V
I
I
OUT
I
BB
T
stg
T
SOL
Conditions
V
EE
= 0 V
V
EE
= 0 V, V
I
≤
V
DD
Continuous surge
—
—
<2 s to 3 s at 248 °C
Min
0
0
50
–0.5
–65
—
Max
5
5
100
0.5
150
265
Unit
V
V
mA
mA
°C
°C
4.1 Handling Precautions
Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere
employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to
determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit
parameters used in each of the models, as defined by JEDEC’s JESD22-A114 (HBM) and JESD22-C101 (CDM)
standards.
Table 4-2. ESD Tolerance
Device
HBM
LCK4310
>2,000 V
Minimum Threshold
CDM
>1,000 V
4
Agere Systems Inc.
Data Sheet
April 20, 2004
4.2 Thermal Parameters (Definitions and Values)
LCK4310
Low-Voltage PLL Clock Driver
System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal
characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they
can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 °C, temperature activated
failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system
designer choose the best package for their applications, including allowing the system designer to thermally design and in-
tegrate their systems.
It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle
size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
Θ
JA
- Junction to Air Thermal Resistance
Θ
JA
is a number used to express the thermal performance of a part under JEDEC standard natural convection conditions.
Θ
JA
is calculated using the following formula:
Θ
JA
= (T
J
– T
amb
) / P; where P = power
Θ
JMA
- Junction to Moving Air Thermal Resistance
Θ
JMA
is effectively identical to
Θ
JA
but represents performance of a part mounted on a JEDEC four layer board inside a wind
tunnel with forced air convection.
Θ
JMA
is reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which
roughly correspond to 1 m/s and 2.5 m/s (respectively).
Θ
JMA
is calculated using the following formula:
Θ
JMA
= (T
J
– T
amb
) / P
Θ
JC
- Junction to Case Thermal Resistance
Θ
JC
is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the
heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top
of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit.
Θ
JC
is calculated using
the following formula:
Θ
JC
= (T
J
– T
C
) / P
Table 4-3. Thermal Parameter Values
Parameter
Θ
JA
Θ
JMA
(500 lf/m)
Θ
JC
63.5
43.5
27.3
Temperature °C/Watt
Agere Systems Inc.
5
FPGA/CPLD
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