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74HC173; 74HCT173
Quad D-type flip-flop; positive-edge trigger; 3-state
Rev. 3 — 8 November 2016
Product data sheet
1. General description
The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device
features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable
(OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the
state of their corresponding Dn inputs that meet the set-up and hold time requirements on
the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the
device to go into a hold mode, outputs hold their previous state independently of clock and
data inputs. A HIGH on MR forces the outputs LOW independently of clock and data
inputs. A HIGH on either output enable pin causes the outputs to assume a
high-impedance OFF-state. Operation of the output enable inputs does not affect the state
of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC173: CMOS level
For 74HCT173: TTL level
Gated input enable for hold (do nothing) mode
Gated output enable control mode
Edge-triggered D-type register
Asynchronous master reset
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74HC173; 74HCT173
Quad D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC173D
74HCT173D
74HC173DB
74HCT173DB
74HC173PW
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT173
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 8 November 2016
2 of 20
NXP Semiconductors
74HC173; 74HCT173
Quad D-type flip-flop; positive-edge trigger; 3-state
Fig 4.
Logic diagram
74HC_HCT173
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 8 November 2016
3 of 20
NXP Semiconductors
74HC173; 74HCT173
Quad D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
OE1, OE2
Q0, Q1, Q2, Q3
CP
GND
E1, E2
D0, D1, D2, D3
MR
V
CC
Pin description
Pin
1, 2
3, 4, 5, 6
7
8
9, 10
14, 13, 12, 11
15
16
Description
output enable input (active LOW)
3-state flip-flop output
clock input (LOW-to-HIGH, edge triggered)
ground (0 V)
data enable input (active LOW)
data input
asynchronous master reset (active HIGH)
supply voltage
74HC_HCT173
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 8 November 2016
4 of 20
PCB设计
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