HV20420
HV20620
Low Charge Injection
8-Channel High Voltage Analog Switch
Ordering Information
Package Options
V
PP
– V
NN
200V
200V
28-pin
plastic DIP
HV20420P
–
28-lead plastic
chip carrier
HV20420PJ
HV20620PJ
Die
HV20420X
–
Features
s
HVCMOS
®
technology for high performance
s
Low charge injection
s
Very low quiescent power dissipation – 10µA
s
Output On-resistance typically 22 ohms
s
Low parasitic capacitances
s
DC to 10MHz analog signal frequency
s
-60dB typical output off isolation at 5MHz
s
CMOS logic circuitry for low power
s
Excellent noise immunity
s
On-chip shift register, latch and clear logic circuitry
s
Flexible high voltage supplies
s
Surface mount package available
General Description
Not recommended for new designs. Please use HV202 instead.
This device is a low charge injection 8-channel high-voltage
analog switch integrated circuit (IC) intended for use in applica-
tions requiring high voltage switching controlled by low voltage
control signals, such as ultrasound imaging and printers. Input
data is shifted into an 8-bit shift register which can then be
retained in an 8-bit latch. To reduce any possible clock feed-
through noise, Latch Enable Bar (LE) should be left high until all
bits are clocked in. Using HVCMOS technology, this switch
combines high voltage bilateral DMOS switches and low power
CMOS logic to provide efficient control of high voltage analog
signals.
This IC is suitable for various combinations of high voltage
supplies, e.g., V
PP
/V
NN
: +50V/–150V, or +100V/–100V.
The specifications for the HV204 and HV206 are identical except
that the pinouts in the 28-lead plastic chip carrier are different.
Absolute Maximum Ratings*
V
DD
Logic power supply voltage
V
PP
- V
NN
Supply voltage
V
PP
Positive high voltage supply
V
NN
Negative high voltage supply
Logic input voltages
Analog Signal Range
Peak analog signal current/channel
Storage temperature
Power dissipation
-0.5V to +18V
220V
-0.5V to V
NN
+200V
+0.5V to -200V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
3.0A
-65°C to +150°C
1.2W
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
13-32
HV20420/HV20620
DC Characteristics
(over recommended operating conditions unless otherwise noted)
0
°
C
Characteristics
Small Signal Switch (ON)
Resistance
Sym
min
max
30
25
25
18
Small Signal Switch (ON)
Resistance Matching
Large Signal Switch (ON)
Resistance
Switch Off Leakage
Per Switch
DC Offset Switch Off
DC Offset Switch On
Pos. HV Supply Current
Neg. HV Supply Current
Pos. HV Supply Current
Neg. HV Supply Current
Switch Output
Peak Current
Output Switch Frequency
f
SW
8.1
I
PP
Supply Current
I
PP
5.0
8.1
I
NN
Supply Current
Logic Supply
Average Current
Logic Supply
Quiescent Current
Data Out Source Current
Data Out Sink Current
Logic Input Capacitance
I
NN
I
DD
I
DDQ
I
SOR
I
SINK
C
IN
0.45
0.45
10
5.0
6.0
10
0.45
0.45
0.70
0.70
10
4.0
I
PPQ
I
NNQ
I
PPQ
I
NNQ
3.0
∆R
ONS
R
ONL
I
SOL
5.0
300
500
20
min
+25
°
C
typ
26
22
22
18
5.0
15
1.0
100
100
10
-10
10
-10
3.0
10
300
500
50
-50
50
-50
2.0
50
8.8
6.3
8.8
6.3
6.0
10
0.40
0.40
10
10.0
6.9
10.0
6.9
6.0
10
mA
mA
µA
mA
mA
pF
V
OUT
= V
DD
- 0.7V
V
OUT
= 0.7V
mA
2.0
15
300
500
max
32
27
27
20
20
+70
°
C
min
max
35
32
30
23
20
%
ohms
µA
mV
mV
µA
µA
µA
µA
A
KHz
ohms
Units
Test Conditions
I
SIG
= 5mA
I
SIG
= 5mA
V
PP
= + 50V,
V
PP
= +100V,
Electrical Characteristics
R
ONS
I
SIG
= 200mA V
NN
= -150V
I
SIG
= 200mA V
NN
= -100V
I
SW
= 5mA, V
PP
= +100V,
V
NN
= -100V
V
SIG
= V
PP
- 10V, I
SIG
= 1.0A
V
SIG
= V
PP
- 10V
to V
NN
+10V
R
L
= 100KΩ
R
L
= 100KΩ
ALL SWs OFF
ALL SWs OFF
ALL SWs ON I
SW
= 5mA
ALL SWs ON I
SW
= 5mA
V
SIG
duty cycle
≤
0.1%
Duty Cycle = 50%
V
PP
= +50V,
V
NN
= -150V
V
PP
= +100V,
V
NN
= -100V
V
PP
= +50V,
V
NN
= -150V
V
PP
= +100V,
V
NN
= -100V
f
CLK
= 3MHz
50KHz
Output
Switching
Frequency
with no
load
13
13-33
HV20420/HV20620
Electrical Characteristics
AC Characteristics
(over operating conditions V
DD
= 15V, unless otherwise noted)
0
°
C
Characteristics
Time to Turn Off V
SIG
*
Set Up Time Before LE Rises
Time Width of LE
Clock Delay Time to Data Out
Time Width of CL
Set Up Time Data to Clock
Hold Time Data from Clock
Clock Freq
Turn On Time
Turn Off Time
Maximum V
SIG
Slew Rate
Sym
t
SIG(OFF)
t
SD
t
WLE
t
DO
t
WCL
t
SU
t
H
f
CLK
t
ON
t
OFF
dv/dt
13
-30
Off Isolation
KO
-45
Switch Crosstalk
Output Switch Isolation
Diode Current
Off Capacitance SW to GND
On Capacitance SW to GND
Output Voltage Spike
K
CR
I
ID
C
SG(OFF)
C
SG(ON)
+V
SPK
-V
SPK
*Time required for analog signal to turn off before output switch turns off.
min
max
min
0
+25
°
C
typ
max
min
+70
°
C
max
Units
ns
Test Condition
150
150
175
150
15
35
5.0
5.0
5.0
150
150
175
150
15
35
5.0
5.0
5.0
13
8.0
150
150
190
150
20
35
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
MHz
µs
µs
50% duty cycle
f
DATA
= f
CLK
/2
V
SIG
= V
PP
- 10V
V
SIG
= V
PP
- 10V
V
PP
= +50V
V
NN
= -150V
V/ns
V
PP
= +100V
V
NN
= -100V
f = 5.0 MHz,
1KΩ//15pF load
f = 5MHz,
50Ω load
f = 5MHz,
50Ω load
300ns pulse width,
2.0% duty cycle
0V, 1MHz
0V, 1MHz
V
PP
= +100V
V
NN
= -100V
R
L
= 50Ω
-30
-45
-60
300
-33
-60
-70
300
-30
-45
-60
300
5.0
25
17
50
dB
dB
dB
mA
pF
pF
mV
-60
5.0
25
17
50
5.0
25
12
38
150
150
17
50
Operating Conditions*
Symbol
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Notes:
1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2 V
SIG
must be V
NN
≤
V
SIG
≤
V
PP
or floating during power up/down transistion.
3 Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than 1.0msec.
Parameter
Logic power supply voltage
1,3
Positive high voltage supply
1,3
Negative high voltage supply
1,3
High-level input voltage
Low-level input voltage
Analog signal voltage peak to peak
2
Operating free air-temperature
Value
10.0V to 15.5 V
50V to V
NN
+ 200V
-100V to -150V
V
DD
-2V to V
DD
0V to 2.0V
V
NN
+10V to V
PP
-10V
0°C to 70°C
13-34
HV20420/HV20620
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
HOLD PREVIOUS STATE
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate
independently.
2. Serial data is clocked in on
the L→ H transition CLK.
3. The switches go to a state
retaining their present
condition at the rising edge of
LE. When LE is low the shift
register data flows through
the latch.
4. D
OUT
is high when switch 7 is
on.
5. Shift register clocking has no
effect on the switch states if
LE is H.
6. The clear input overrides all
other inputs.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Test Circuits
V
PP
–10V
V
PP
–10
I
SOL
R
L
10KΩ
V
OUT
V
OUT
V
NN
+10
100KΩ
R
L
V
PP
V
NN
V
PP
V
NN
V
DD
GND
15V
V
PP
V
NN
V
PP
V
NN
V
DD
GND
15V
V
PP
V
NN
V
PP
V
NN
V
DD
GND
15V
Switch OFF Leakage
DC Offset ON/OFF
T
ON
/T
OFF
Test Circuit
13
V
IN
= 10 V
P–P
@5MHz
+V
SPK
V
OUT
–V
SPK
50Ω
NC
V
IN
= 10 V
P–P
@5MHz
50Ω
50Ω
1K
V
OUT
R
L
V
PP
V
NN
V
PP
V
NN
V
DD
GND
V
OUT
V
IN
15V
V
PP
V
NN
V
PP
V
NN
V
DD
GND
15V
V
PP
V
NN
V
PP
V
NN
V
DD
GND
V
OUT
V
IN
15V
K
O
= 20Log
K
CR
= 20Log
OFF Isolation
Output Voltage Spike
Crosstalk
13-35
HV20420/HV20620
Logic Timing Waveforms
D
N – 1
DATA
IN
50%
D
N
50%
D
N + 1
LE
50%
50%
t
WLE
t
SD
50%
t
SU
t
h
t
DO
50%
CLOCK
DATA
OUT
50%
t
OFF
t
ON
VOUT
(TYP)
OFF
ON
90%
10%
CLR
50%
t
WCL
50%
Logic Diagram
LATCHES
D
IN
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
CLK
SW1
SW2
SW3
8 BIT
SHIFT
REGISTER
SW4
SW5
D
OUT
SW6
SW7
V
NN
V
PP
V
DD
LE
CL
13-36
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