CT1820
Data Terminal Bit Processor
for MIL-STD-1553 A & B
www.aeroflex.com/Avionics
April 10, 2008
FEATURES
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
❑
Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to MIL-STD-1553
specifications, including Address, Mode Code and Broadcast Decoding and Terminal Fail Safe
Flexibility - all control lines accessible
Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems
Dual rank l/O registers for versatile subsystem tlmlng
Operates from +5VDC @ 50mA
Self-contained +5Vdc oscillator and clock driver @ 13 mA
Look-ahead serial receive data output
Self-test, on-line wraparound, plus off-line capability
Full military (-55°C to +125°C) temperature range
Designed for commercial, industrial and aerospace applications
MIL-PRF-38534 compliant
Packaging – Metal hermetic
- 56 pin, plug-in, 1.155"W x 2.155"L x .200"Ht
- 60 lead, flat-pack, 1.015"W x 1.59"L x .147"Ht
DESC Standard microcircuit drawing (SMD): 5962-90636
❑
DESCRIPTION
The Aeroflex Plainview CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the
interface between a MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal
parallel data bus. The unit can be employed as the mux bus interface for Remote Subsystems or Master Terminal
Bus Controllers, thus providing a common interface for all systems communicating over the bus.
The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status
and Data words from the bus to parallel output lines, together with error information, bus status and
handshaking signals. It also contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal
Fail Safe Signal and Self Test.
In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words,
under subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation
between the unit and the subsystem for direct data flow.
The hybrid is completely compatible with all the electrical and functional specification requirements of
MIL-STD-1553 A & B.
SCDCT1820 Rev F
7
45
46
47
48
50
44
41
42
2
3
4
5
6
54
56
56
43
43
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
53
43
DATA
SELECT 2
(LSB) D0
LATCH
DATA
2
DATA SELECT 1
(MSB) D15
(OPTIONAL)
SERIAL
INPUT
LATCH DATA 1
LOAD
DATA 2
LOAD DATA 1
43
Vcc
+5V
GND
GND
SCDCT1820 Rev F 4/10/08
SECOND
RANK
REC’V
REG
D0 - D7
FIRST
RANK
XMT
REG
DO - D7
SECOND
RANK
XMT
REG
DO - D7
1
11
34
SECOND
RANK
REC’V
REG
D8 - D15
FIRST
RANK
XMT
REG
D8 - D15
SECOND
RANK
XMT
REG
D8 - D15
CASE
20
DATA IN
DATA IN
BUILT IN
TEST
SELECT
21
22
BIT SELECT
DATA OUT
DATA OUT
19
25
26
MANCHESTER
DECODER
&
CONTROL LOGIC
MANCHESTER
ENCODER
&
CONTROL LOGIC
FAIL SAFE
15
SEND DATA
ESCOUT
SYNC SEL
ENC ENA
OUTPUT INH
MRST
+5V OSC / CLOCK POWER
XTAL
CLOCK OUT
FAIL SAFE
TIMER
&
CONTROL
27
28
24
23
35
38
30
29
18
OSC
&
CLOCK
DRIVER
CLOCK IN
17
FIRST
RANK
REC’V
REG
D0 - D7
FIRST
RANK
REC’V
REG
D8 - D15
36
SERIAL DATA OUT
32
RT ENABLE
12
(MSB) A4
8
A3
A2
5 BIT
ADDRESS
9
A1
ADDRESS
DECODE
10
{
13
(LSB) A0
2
39
BROADCAST
BROAD-
CAST
DECODE
40
MODE CODE
MODE
CODE
DECODE
14
VALID WORD
16
COMM/DATA SYNC
33
DEC RST
37
TAKE DATA
31
DSC OUT
Aeroflex Plainview
Figure 1 – FUNCTIONAL DIAGRAM
(Plug-in Pins shown)
RX
DATA
IN
32
25
33
1
TX
DATA
IN
TX
DATA
IN
DATA
OUT
DATA
OUT
25
DATA
26
TX
DATA
OUT
DATA
BUS
TX
DATA
OUT
CT1820
BIT
PROCESSOR
16 BIT
OR
8 BIT
SUB-
SYSYEM
12
MHz
22
CT3231
T/R
HYBRID
2
7
RX
DATA
OUT
DATA
IN
DATA
IN
21
29
XTAL
26
RX
DATA
IN
31
RX
DATA
10
OUT
CONTROL
TX
INHIBIT
Figure 2 – TYPICAL MIL-STD-1553 DATA TERMINAL
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Logic Input Voltage
Clock Output Current (Pin 18 - Plug-in)
Clock In (Pin 17 - Plug-in)
Storage Temperature Range
Operating Case Temperature Range
Range
+7.0
-0.3 to +5.5
15
-0.3 to VCC +0.3V
-65 to +150
-55 to +125
Units
V
V
mA
V
°C
°C
ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V ±10%, T
C
= -55°C to +125°C)
Sym
V
IH
V
IL
V
OH
V
OL
V
IHC
V
ILC
V
OHC
V
OLC
l
OC
l
OSC
Parameter / Conditions
Logic "1" Input Voltage
Logic "0" Input Voltage
Logic "1" Output Voltage
Logic "0" Output Voltage
Logic "1" Input Voltage (CLOCK)
Logic "0" Input Voltage (CLOCK)
Logic "1" Output Voltage (CLOCK)
Logic "0" Output Voltage (CLOCK)
Logic Supply Current
Oscillator / Clock Supply Current
Min
2.0
-
Typ
-
-
Max
-
0.7
Units
V
V
See Pin assignments and Loading
See Pin assignments and Loading
V
CC
-0.5
-
V
CC
-0.3
-
-
-
8
-
GND+0.5
-
GND+0.3
50
13
V
V
V
V
mA
mA
SCDCT1820 Rev F 4/10/08
Aeroflex Plainview
3
ELECTRICAL CHARACTERISTICS – PIN ASSIGNMENTS AND LOADING
In the following table, the symbols are defined as follows:
I
IH
= maximum input HIGH current with V
IH
= 2.5 volts
I
IL
= maximum input LOW current with V
IL
= 0.4 volts
I
OH
= maximum output HIGH current for V
OH
= 2.5 volts minimum
I
OL
= maximum output LOW current for V
OL
= 0.4 volts maximum
* Indicates use of an internal pull-up resistor
Pin No
Plug
in
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Flat
Pack
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
38
39
VCC
D8
D9
D10
D11
D12
DATA SELECT 1
A3*
A2*
A1*
GROUND
A4*
A0*
VALID WORD
FAIL SAFE
COMM / DATA SYNC
CLOCK IN
CLOCK OUT
S/T SELECT
CASE
DATA IN
DATA IN
ENC ENA
SYNC SEL
DATA OUT
DATA OUT
SEND DATA
ESC OUT
XTAL
+5V (OSC/CLOCK)
DSC OUT
RT ENABLE
-1000 1.2
-400
4.0
1.2
4.0
20
20
20
20
-0.4
-0.4
-0.4
-0.4
-400
-400
-400
4.0
4.0
4.0
4.0
4.0
4.0
1.2
20
-0.4
+100 +0.1
-1000 1.0
1.0
-400
-400
-400
4.0
4.0
4.0
4.0
4.0
4.0
20
-0.4
Logic and power return
MSB of 5 Bit ADDRESS INPUT
LSB of 5 Bit ADDRESS INPUT
A LOW on this output indicates receipt of avalid word
A HIGH on this output indicates termination of a transmitted message
that exceeds 768μs.
A HIGH on this output indicates COMMAND (or STATUS) word
reception. A LOW indicates DATA word reception.
Input for 12MHz clock (20pf load).
Output of OSCILLATOR AND CLOCK DRIVER.
A HIGH on this input sets the unit in the self test mode.
CASE CONNECTION
A HIGH on this input represents a positive state on the bus.
A HIGH on this input represents a negative state on the bus. (Pins 21
and 22 must both be high when the bus is inactive.)
A LOW on this input initiates a transmit cycle.
Actuates COMMAND (or STATUS) sync for an input LOW and DATA
sync for an input HIGH.
A HIGH on this output produces a positive state on the bus.
A HIGH on this output produces a negative state on the bus.
A HlGH on this output indicates data shifting during the transmit cycle.
LOW to HIGH transitions on thls output during HIGH SEND DATA cause
the transmit cycle data shifting to occur.
A 12MHz (parallel resonant) crystal is connected between this pin and
ground.
+5V power for OSCILLATOR AND CLOCK POWER DRIVER.
LOW to HIGH transitions on this output during LOW TAKE DATA cause
receive cycle data shifting to occur.
A HIGH on this output indicates reception of a valid COMMAND (or
STATUS) word containing the terminalís address. It also resets the FAIL
SAFE.
20
20
-0.4
-0.4
A LOW on this input applies the contents of the SECOND RANK REC’V
REG to the D8-D15 I/O pins
Part of 5 Bit ADDRESS INPUT
Name
CT1820
I
IH
I
IL
(μA) (mA)
-
20
-
I
OH
I
OL
(μA) (mA
-
-
CT1820-2
I
OL
(mA)
-
10.0
+5V Power Input
Part of 16 Bit TRI-STATE l/O
Description
-0.4 -1000 6.0
-1000 1.2
SCDCT1820 Rev F 4/10/08
Aeroflex Plainview
4
ELECTRICAL CHARACTERISTICS – PIN ASSIGNMENTS AND LOADING con’t
In the following table, the symbols are defined as follows:
I
IH
= maximum input HIGH current with V
IH
= 2.5 volts
I
IL
= maximum input LOW current with V
IL
= 0.4 volts
I
OH
= maximum output HIGH current for V
OH
= 2.5 volts minimum
I
OL
= maximum output LOW current for V
OL
= 0.4 volts maximum
* Indicates use of an internal pull-up resistor
Pin No
Plug
in
33
Flat
Pack
40
DEC RST
Name
CT1820
I
IH
I
IL
(μA) (mA)
20
-0.4
I
OH
I
OL
(μA) (mA
CT1820-2
I
OL
(mA)
A LOW on this input (for 1µs minimum) resets the decoder to a condition ready for
a new word, resets the COMM / DATA SYNC output LOW, and resets the VALID
WORD output HIGH.
Description
34
35
36
37
38
41
42
43
44
45
GROUND
OUTPUT INH
SERIAL DATA OUT
TAKE DATA
MRST
20
-0.4
20
-0.4
-400
-400
4.0
4.0
4.0
4.0
Logic and Power Return.
A LOW on this input holds output pins 25 and 26 LOW.
The received serial data in NRZ format is available at this pin during
LOW TAKE DATA.
A LOW on this output indicates data shifting during the receive cycle.
A LOW on this input (for 1μs minimum) interrupts and clears the
transmit cycle, resets the FAIL SAFE, and also performs the same
functions as DEC RST.
-400
-600
4.0
6.0
4.0
6.0
A HIGH on this output indicates reception of a valid COMMAND (or
STATUS) word containing all ONES in the address field.
A LOW on this output indicates reception of a valid COMMAND (or
STATUS) word containing all ONES or all ZEROS in the sub-address
field.
Part of 16 Bit TRI-STATE l/O
39
40
46
47
BROADCAST*
MODE CODE*
41
42
43
44
45
46
47
48
49
48
49
50
51
52
53
54
55
56
D6
D7
DATA SELECT 2
D5
D0
D1
D2
D3
LATCH DATA 2
20
-0.4 -1000 6.0
10.0
20
20
-0.4
-0.4 -1000 6.0
10.0
A LOW on this input applies the contents of the SECOND RANK REC’V
REG to the D0-D7 I/O pins.
Part of 16 Bit TRI-STATE l/O
LSB of 16BIT TRI-STATE I/O
Part of 16 Bit TRI-STATE l/O
Part of 16 Bit TRI-STATE l/O
Part of 16 Bit TRI-STATE l/O
-0.4
A HIGH on this input allows the l/O data on D0-D7 to appear at the
output of the FIRST RANK XMT REG. A LOW on this input holds the
register outputs in their last state.
10.0
Part of 16 Bit TRl-STATE l/O
A LOW on this input loads the D0-D7 data into the SECOND RANK XMT
REG. A HIGH on this input then locks out the data inputs to permit serial
shifting.
A HIGH on this input allows the l/O data on D8-D15 to appear at the
output of the FIRST RANK XMT REG. A LOW on this input holds the
register outputs in their last state.
50
51
57
58
D4
LOAD DATA 2
-0.4 -1000 6.0
-0.4
52
59
LATCH DATA 1
53
2
LOAD DATA 1
20
-0.4
A LOW on this input loads the D8-D15 data into the SECOND RANK
XMT REG. A HIGH on this input then locks out the data inputs to permit
serial shifting.
10.0
Part of 16 Bit TRl-STATE l/O.
OPTIONAL SERIAL INPUT.
54
55
56
-
-
-
-
3
4
5
1
30
31
60
D13
D14
D15
NC
NC
NC
NC
-
-
-
-
-0.4 -1000 6.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
No Contact
SCDCT1820 Rev F 4/10/08
Aeroflex Plainview
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
