1 MEG x 18, 512 x 36
2.5V V
DD
, HSTL, PIPELINED DDRb2 SRAM
18Mb DDR SRAM
2-Word Burst
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fast cycle times
Pipelined, double data rate operation
Single 2.5V ±0.1V power supply (V
DD
)
Separate isolated output buffer supply (V
DD
Q)
JEDEC-standard 1.5V to 1.8V (±0.1V) HSTL I/O
User-selectable trip point with V
REF
HSTL programmable impedance outputs
synchronized to optional dual-data clocks
Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
JTAG boundary scan
Fully-static design for reduced-power standby
Clock-stop capability
Common data inputs and data outputs
Low-control ball count
Internally self-timed, registered LATE WRITE cycles
Linear burst order with four-tick burst counter
13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA
package
Full data coherency, providing most current data
MT57V1MH18A
MT57V512H36A
Figure 1: 165-Ball FBGA
Table 1:
Valid Part Numbers
DESCRIPTION
1 Meg x 18, DDRb2 SRAM
512K x 36, DDRb2 SRAM
PART NUMBER
MT57V1MH18AF-xx
MT57V512H36AF-xx
Options
• Clock Cycle Timing
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
1 Meg x 18
512K x 36
• Operating Temperature Range
Commercial (0°C
£
T
A
£
70°C)
• Package
165-ball, 13mm x 15mm FBGA
NOTE:
Marking
-5
-6
-7.5
1
General Description
MT57V1MH18A
MT57V512H36A
None
F
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
The Micron
®
DDR synchronous SRAM employs
high-speed, low-power CMOS designs using an
advanced 6T CMOS process.
The DDR SRAM integrates an 18Mb SRAM core with
advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by an input clock pair (K and K#)
and are latched on the rising edge of K and K#. The
synchronous inputs include all addresses, all data
inputs, active LOW load (LD#) and read/write (R/W#).
Write data is registered on the rising edges of both K
and K#. Read data is driven on the rising edge of C and
C# if provided, or on the rising edge of K and K#, if C
and C# are not provided.
Asynchronous inputs include impedance match
(ZQ). Synchronous data outputs (Q) are closely
matched to the two echo clocks (CQ and CQ#), which
can be used as data receive clocks. Output data clocks
(C and C#) are also provided for maximum system
clocking and data synchronization flexibility.
18Mb: 2.5V V
DD
, HSTL, Pipelined DDRb2 SRAM
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
1
©2003 Micron Technology, Inc.
1 MEG x 18, 512 x 36
2.5V V
DD
, HSTL, PIPELINED DDRb2 SRAM
Additional write registers are incorporated to
enhance pipelined WRITE cycles and reduce READ-to-
WRITE turnaround time. WRITE cycles are self-timed.
The device does not utilize internal phase-locked
loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
The device can be used in HSTL systems by supply-
ing an appropriate reference voltage (V
REF
). The
device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.
The SRAM operates from a 2.5V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP and other applications that benefit from a very
,
wide, high-speed data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
NO OPERATION (NOP) cycle when transitioning from
a READ to a WRITE cycle. At higher frequencies, a sec-
ond NOP cycle may be required to prevent bus conten-
tion. NOP cycles
a
re not required when switching from
a WRITE to a READ.
If a READ occurs after a WRITE cycle, address and
data for the WRITE are stored in registers. The write
information must be stored because the SRAM cannot
perform the last word write to the array without con-
flicting with the READ. The data stays in this register
until the next WRITE cycle occurs. On the first WRITE
cycle after the READ(s), the stored data from the earlier
WRITE will be written into the SRAM array. This is
called a posted write.
A read can be made immediately to an address even
if that address was written in the previous cycle. Dur-
ing this READ cycle, the SRAM array is bypassed, and
data is read instead from the data register storing the
recently written data. This is transparent to the user.
This feature facilitates system data coherency.
The DDR SRAM differs in some ways from its prede-
cessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. In addi-
tion to the echo clocks, two single-ended input clocks
are available (C and C#). The SRAM synchronizes its
output data to these data clock rising edges if pro-
vided. If not present, C and C# must be tied HIGH and
output timing is derived from K and K#. No differential
clocks are used in this device. This clocking scheme
provides greater system tuning capability than Clay-
more SRAMs and reduces the number of input clocks
required by the bus master.
DDR Operation
The DDR SRAM enables high performance opera-
tion through high-clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
18Mb: 2.5V V
DD
, HSTL, Pipelined DDRb2 SRAM
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology Inc.
1 MEG x 18, 512 x 36
2.5V V
DD
, HSTL, PIPELINED DDRb2 SRAM
Programmable Impedance Output
Buffer
The DDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance is
one-fifth the value of RQ (within 15 percent), the range
of RQ is 175
W
to 350
W
. Alternately, the ZQ ball can be
connected directly to V
DD
Q, which will place the
device in a minimum impedance mode.
Output impedance updates may be required
because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. An update
o
f the impedance is transparent to
the system. Impedance updates do not affect device
operation, and all data sheet timing and current speci-
fications are met during an update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
Clocking
The DDR SRAM supports flexible clocking
approaches. C and C# may be supplied to the SRAM to
synchronize data output across multiple devices,
enabling the bus master to receive all data simulta-
neously. If C and C# are not provided (tied HIGH) K
and K# are used as the output timing reference.
The echo clocks (CQ and CQ#) provide another
alternative for data synchronization. The echo clocks
are controlled exactly like the DQ signals except that
CQ and CQ# have an additional small delay for easier
data capture by the bus master. Echo clocks must be
separately received for each SRAM in the system. Use
of echo clocks maximizes the available data window
for each SRAM in the system.
The output echo clocks are precise references to
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
18Mb: 2.5V V
DD
, HSTL, Pipelined DDRb2 SRAM
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology Inc.
1 MEG x 18, 512 x 36
2.5V V
DD
, HSTL, PIPELINED DDRb2 SRAM
Figure 2: Functional Block Diagram
1 Meg x 18; 512K x 36
n
SA
LD#
n
E
ADDRESS
REGISTER
COMPARE
(NOTE 2)
n
SA0 D0
CLK
n-1
Q0 SA0’
n
READ
BURST
LOGIC
(NOTE 1)
WRITE#
n
WRITE#
SA0''
C
SA’
C#
OUTPUT
CONTROL
LOGIC
SA0'''
K
a
WRITE
E ADDRESS
REGISTER
INPUT
REGISTER
E
a
a
INPUT
REGISTER
E
n
SA0’
SA0#’
SA0’
a
CLK
WRITE
REGISTER
a
WRITE
DRIVER
a
a
SA0#’
SA0’
2
n
x a
MEMORY
ARRAY
a
SENSE
AMPS
a
a
C
a
OUTPUT
REGISTER
a
0
ZQ
a
a
OUTPUT
BUFFER
E
a
2:1
MUX
a
1
2
CQ, CQ#
DQ
a
a
a
K#
0
1
a
SA0''’
a
OE
REGISTER
C
R/W#
BWx#
R/W#
E REGISTER
WRITE#
NOTE:
1. SA0 is advanced in linear burst order at each K and K# rising edge.
2. The compare width is n – 1 bits. The compare is performed only if a WRITE is pending and a READ cycle is requested.
If the address matches, data is routed directly to the device outputs, bypassing the memory array.
3. Figure 2 illustrates simplified device operation. See truth tables, ball descriptions, and timing diagrams for detailed
information.
4. CQ and CQ# do not tri-state except during some JTAG test modes.
5. For 1 Meg x 18, n = 20 and a = 18.
For 512K x 36, n = 19 and a = 36.
18Mb: 2.5V V
DD
, HSTL, Pipelined DDRb2 SRAM
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology Inc.
1 MEG x 18, 512 x 36
2.5V V
DD
, HSTL, PIPELINED DDRb2 SRAM
Figure 3: Application Example
R = 250Ω
R = 250Ω
SRAM 1
DQ
SA
ZQ
CQ
CQ#
DQ
SA
SRAM 2
ZQ
CQ
CQ#
LD# R/W# C C# K K#
LD# R/W# C C# K K#
DQ
Address
Cycle Start#
R/W#
Vt
R
Vt
BUS
SRAM 1 Input CQ#
MASTER
SRAM 2 Input CQ
(CPU
SRAM 2 Input CQ#
or
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
SRAM 1 Input CQ
NOTE:
1. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
2. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
3. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
18Mb: 2.5V V
DD
, HSTL, Pipelined DDRb2 SRAM
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology Inc.
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