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46DR16640A: 产品描述Clock frequency up to 400MHz; 文件大小864KB，共28页; 制造商ISSI(芯成半导体); 官网地址http://www.issi.com/

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46DR16640A概述

Clock frequency up to 400MHz

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IS43/46DR81280A, IS43/46DR16640A

1Gb (x8, x16) DDR2 SDRAM

FEATURES



Clock frequency up to 400MHz

8 internal banks for concurrent operation

4‐bit prefetch architecture

Programmable CAS Latency: 3, 4, 5, 6 and 7

Programmable Additive Latency: 0, 1, 2, 3, 4, 5

and 6

Write Latency = Read Latency‐1

Programmable Burst Sequence: Sequential or

Interleave

Programmable Burst Length: 4 and 8

Automatic and Controlled Precharge Command

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 7.8 s (8192 cycles/64 ms)

OCD (Off‐Chip Driver Impedance Adjustment)

ODT (On‐Die Termination)

Weak Strength Data‐Output Driver Option



Bidirectional differential Data Strobe (Single‐

ended data‐strobe is an optional feature)

On‐Chip DLL aligns DQ and DQs transitions with

CK transitions

DQS# can be disabled for single‐ended data

strobe

Read Data Strobe supported (x8 only)

Differential clock inputs CK and CK#

VDD and VDDQ = 1.8V ± 0.1V

PASR (Partial Array Self Refresh)

SSTL_18 interface

tRAS lockout supported

Operating temperature:

Commercial (T

= 0°C to 70°C ; T

= 0°C to 85°C)

Industrial (T

= ‐40°C to 85°C; T

= ‐40°C to 95°C)

Automotive, A1 (T

= ‐40°C to 85°C; T

= ‐40°C to 95°C)

Automotive, A2 (T

= ‐40°C to 105°C; T

= ‐40°C to

105°C)

SEPTEMBER 2011

OPTIONS

ADDRESS TABLE

Parameter

Row Addressing

Column Addressing

Bank Addressing

Precharge Addressing

128Mx8

A0‐A13

A0‐A9

BA0‐BA2

A10

64Mx16

A0‐A12

A0‐A9

BA0‐BA2

A10



Configuration:



128Mx8 (16M x 8 x 8 banks)



64Mx16 (8M x 16 x 8 banks)



Package:



60‐ball TW‐BGA for x8



84‐ball TW‐BGA for x16

Clock Cycle Timing

Speed Grade

CL‐tRCD‐tRP

tCK (CL=3)

tCK (CL=4)

tCK (CL=5)

tCK (CL=6)

tCK (CL=7)

Frequency (max)

‐37C

DDR2‐533C

4‐4‐4

3.75

266

‐3D

DDR2‐667D

5‐5‐5

3.75

333

‐25E

DDR2‐800E

6‐6‐6

3.75

2.5

400

‐25D

DDR2‐800D

5‐5‐5

3.75

2.5

400

Units

tCK

MHz

Note: The ‐37C device specification is shown for reference only.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

– www.issi.com –

Rev. D, 08/30/2011

IS43/46DR81280A, IS43/46DR16640A

Functional Description

Power‐up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may

result in undefined operation.

Power‐up and Initialization Sequence

The following sequence is required for Power‐up and Initialization.

1. Either one of the following sequence is required for Power‐up:

A. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT

at a LOW state (all other inputs may be

undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to

VDD(Min); and during the VDD voltage ramp, |VDD‐VDDQ|

≥

0.3 V. Once the ramping of the supply voltages is

complete (when VDDQ crosses VDDQ(Min)), the supply voltage specifications provided in the table Recommended DC

Operating Conditions (SSTL_1.8), prevail.



VDD, VDDL and VDDQ are driven from a single power converter output, AND



VTT is limited to 0.95V max, AND



VREF tracks VDDQ/2, VREF must be within ± 300mV with respect to VDDQ/2 during supply ramp time.



VDDQ ≥ VREF must be met at all times

B. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT

at a LOW state (all other inputs may be

undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch‐

up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC

and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the

ramping of the supply voltages is complete, the supply voltage specifications provided in the table Recommended DC

Operating Conditions (SSTL‐1.8), prevail.



Apply VDD/VDDL before or at the same time as VDDQ.



VDD/VDDL voltage ramp time must be no greater 200 ms from when VDD ramps from 300 mV to VDD(Min) .



Apply VDDQ before or at the same time as VTT.



The VDDQ voltage ramp time from when VDD(Min) is achieved on VDD to the VDDQ(Min) is achieved on VDDQ

must be no greater than 500 ms.

2. Start clock and maintain stable condition.

3. For the minimum of 200 µs after stable power (VDD, VDDL, VDDQ, VREF, and VTT values are in the range of the minimum and

maximum values specified in the table Recommended DC Operating Conditions (SSTL‐1.8)) and stable clock (CK, CK#), then apply

NOP or Deselect and assert a logic HIGH to CKE.

4. Wait minimum of 400 ns then issue a precharge all command. During the 400 ns period, a NOP or Deselect command must be

issued to the DRAM.

5. Issue an EMRS command to EMR(2).

6. Issue an EMRS command to EMR(3).

7. Issue EMRS to enable DLL.

8. Issue a Mode Register Set command for DLL reset.

9. Issue a precharge all command.

10. Issue 2 or more auto‐refresh commands.

11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting

the DLL.)

12. Wait at least 200 clock cycles after step 8 and then execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD

calibration is not used, EMRS Default command (A9=A8=A7=HIGH) followed by EMRS OCD Calibration Mode Exit command

(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).

13. The DDR2 SDRAM is now ready for normal operation.

Note:

1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.

Integrated Silicon Solution, Inc.

– www.issi.com –

Rev. D, 08/30/2011

IS43/46DR81280A, IS43/46DR16640A

Initialization Sequence after Power‐Up Diagram

Programming the Mode Register and Extended Mode Registers

For application flexibility, burst length, burst type, CAS# latency, DLL reset function, write recovery time (WR) are user defined

variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance,

additive CAS latency, ODT (On Die Termination), single‐ended strobe, and OCD (off chip driver impedance adjustment) are also user

defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register

(MR) or Extended Mode Registers EMR[1] and EMR[2] can be altered by re‐executing the MRS or EMRS Commands. Even if the user

chooses to modify only a subset of the MR, EMR[1], or EMR[2] variables, all variables within the addressed register must be

redefined when the MRS or EMRS commands are issued. The x16 option does not have A13, so all references to this address can be

ignored for this option.

MRS, EMRS and Reset DLL do not affect memory array contents, which mean re‐initialization including those can be executed at any

time after power‐up without affecting memory array contents.

DDR2 Mode Register (MR) Setting

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS# latency, burst

length, burst sequence, DLL reset, tWR and active power down exit time to make DDR2 SDRAM useful for various applications. The

default value of the mode register is not defined, therefore the mode register must be written after power‐up for proper operation.

The mode register is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2 while controlling the state of address

pins A0 ‐ A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the mode register. The

mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register

contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in

the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ‐ A2

with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is

defined by A3; CAS latency is defined by A4 ‐ A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is

used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time tWR is defined by A9 ‐ A11. Refer to the

table for specific codes.

Integrated Silicon Solution, Inc.

– www.issi.com –

Rev. D, 08/30/2011

46DR16640A相似产品对比

	46DR16640A	46DR81280A
描述	Clock frequency up to 400MHz	Clock frequency up to 400MHz

46DR16640A

46DR16640A概述

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