256Mb: x8, x16 Automotive DDR SDRAM
Features
Automotive DDR SDRAM
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
Features
• V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
V
DD
= 2.6V ±0.1V, V
DDQ
= 2.6V ±0.1V (DDR400)
1
• Bidirectional data strobe (DQS) transmitted/
received with data, that is, source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths (BL): 2, 4, or 8
• Auto refresh
–
64ms, 8192-cycle(AIT)
–
16ms, 8192-cycle (AAT)
• Self refresh (not available on AAT devices)
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2-compatible)
• Concurrent auto precharge option supported
•
t
RAS lockout supported (
t
RAP =
t
RCD)
• AEC-Q100
• PPAP submission
• 8D response time
Options
• Configuration
–
32 Meg x 8 (8 Meg x 8 x 4 banks)
–
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic package – OCPL
–
66-pin TSOP
–
66-pin TSOP (Pb-free)
• Plastic package
–
60-ball FBGA (8mm x 12.5mm)
–
60-ball FBGA (8mm x 12.5mm)
(Pb-free)
• Timing – cycle time
–
5ns @ CL = 3 (DDR400)
• Self refresh
–
Standard
–
Low-power self refresh
• Temperature rating
–
Industrial (–40qC to +85qC)
–
Automotive (–40qC to +105qC)
• Revision
–
x8, x16
Marking
32M8
16M16
TG
P
CV
CY
-5B
None
L
AIT
AAT
:M
Notes: 1. DDR400 devices operating at < DDR333 con-
ditions can use V
DD
/V
DDQ
= 2.5V +0.2V.
2. Not all options listed can be combined to
define an offered product. Use the Part Cata-
log Search on www.micron.com for product
offerings and availability.
PDF:09005aef848ea6ef/Source: 09005aef845d3b9c
256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev. B 11/11 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x8, x16 Automotive DDR SDRAM
Features
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and
CL = 3 (-5B)
Clock Rate (MHz)
Speed Grade
-5B
-6
6T
-75E/-75Z
-75
CL = 2
133
133
133
133
100
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
Data-Out Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
+0.40ns
+0.40ns
+0.45ns
+0.50ns
+0.50ns
Table 2:
Parameter
Addressing
32 Meg x 8
8 Meg x 8 x 4 banks
8K
8K (A[12:0])
4 (BA[1:0])
1K (A[9:0])
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A[12:0])
4 (BA[1:0])
512 (A[8:0])
Configuration
Refresh count
Row address
Bank address
Column address
Table 3:
Marking
-5B
1
-6
-6T
-75E
-75Z
-75
Speed Grade Compatibility
PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600(2-2-2)
Yes
–
–
–
–
–
-5B
Notes:
Yes
Yes
Yes
–
–
–
-6/-6T
Yes
Yes
Yes
Yes
–
–
-75E
Yes
Yes
Yes
Yes
Yes
–
-75Z
Yes
Yes
Yes
Yes
Yes
Yes
-75
Yes
Yes
Yes
Yes
Yes
Yes
-75
1. The -5B device is backward compatible with all slower speed grades. The voltage range of
-5B device operating at slower speed grades is V
DD
= V
DDQ
= 2.5V ± 0.2V.
PDF:09005aef848ea6ef/Source: 09005aef845d3b9c
256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev. B 11/11 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2011 Micron Technology, Inc. All rights reserved.
256Mb: x8, x16 Automotive DDR SDRAM
Features
Figure 1:
256Mb DDR SDRAM Part Numbers
Example Part Number: MT 4 6 V1 6 M1 6 P - 5 B A IT: M
-
MT46V
Configuration
Package
Speed
:
Sp.
Op. Temp. Revision
Revision
Configuration
32 Meg x 8
16 Meg x 16
32M8
16M16
:M
x8, x16
Operating Temperature
AIT
Automotive Industrial Temp
Package
400-mil TSOP
400-mil TSOP (Pb-free)
8mm x 12.5mm FBGA
8mm x 12.5mm FBGA (Pb-free)
TG
P
CV
CY
AAT Automotive Temp
Special Options
Standard
L
Low power
Speed Grade
-5B
tCK = 5ns, CL = 3
FBGA Part Marking System
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. For a quick conversion of an FBGA code,
see the FBGA Part Marking Decoder on Micron’s Web site:
www.micron.com.
PDF:09005aef848ea6ef/Source: 09005aef845d3b9c
256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev. B 11/11 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2011 Micron Technology, Inc. All rights reserved.
256Mb: x8, x16 Automotive DDR SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Part Marking System 3
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Automotive Industrial Tempature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Automotive Tempature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin and Ball Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Electrical Specifications – I
DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
BURST TERMINATE (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Mode Register 54
Extended Mode Register 57
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Auto Precharge 84
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
PDF:09005aef848ea6ef/Source: 09005aef845d3b9c
256mb_x8x16_at_ddr_t66aTOC.fm - Rev. A; Core DDR Rev. B 11/11 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2011 Micron Technology, Inc. All rights reserved.
256Mb: x8, x16 Automotive DDR SDRAM
State Diagram
State Diagram
Figure 2:
Simplified State Diagram
Power
applied
Power
on
PRE
Precharge
all banks
LMR
Self
refresh
REFS
LMR
REFSX
Idle
REFA
all banks
precharged
CKEL
CKEH
MR
EMR
Auto
refresh
Active
power-
down
ACT
CKE HIGH
Precharge
power-
down
CKE LOW
Row
active
WRITE
WRITE
WRITE A
Write
READ A
READ
READ
BST
READ
Burst
stop
Read
WRITE A
PRE
READ A
PRE
PRE
READ A
Write A
Read A
PRE
Precharge
PREALL
Automatic sequence
Command sequence
ACT = ACTIVE
BST = BURST TERMINATE
CKEH = Exit power-down
CKEL = Enter power-down
EMR = Extended mode register
LMR = LOAD MODE REGISTER
MR = Mode register
PRE = PRECHARGE
PREALL = PRECHARGE all banks
READ A = READ with auto precharge
REFA = AUTO REFRESH
REFS = Enter self refresh
REFSX = Exit self refresh
WRITE A = WRITE with auto precharge
Note:
This diagram represents operations within a single bank only and does not capture concur-
rent operations in other banks.
PDF:09005aef848ea6ef/Source: 09005aef845d3b9c
DDR_x4x8x16_Core1.fm - Core DDR Rev. B 11/11 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2011 Micron Technology, Inc. All rights reserved.
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