SUMMIT
MICROELECTRONICS, Inc.
Dual 10-Bit Nonvolatile DAC
SMP9210, -11, -12
Preliminary
FEATURES
!
Two 10-Bit Nonvolatile DACs
"
INL ±1LSB
"
DNL ±1LSB
!
Programmable Configuration
!
Programmable Power On Reset Options
"
Recall Full Scale Value
"
Recall Zero Scale Value
"
Recall Mid-Scale Value
"
Recall NV Register Value
!
Tandem or Independent Operation of DACs
!
Programmable Power Down Mode (Short VOUT
to GND or Float VOUT)
!
I2C Interface
!
Low Noise Outputs
!
2.7V to 5.5V Operation
!
–40ºC to 85ºC Temperature Range
APPLICATIONS
!
ATE Set and Forget Calibration
!
Laser Biasing
!
RFPA Biasing
SIMPLIFIED APPLICATION DRAWING
I
2
C
SMP9210
VOUT1
3.3V
MONITOR
DIODE
LASER
DIODE
MD
RDAMP
IMOD
APC
MODMON
IN+
IN–
GND
Laser Driver
MODSET
BIASSET
APCSET
VCC
IBIAS
VOUT1
VOUT2
CAPC
1nF
RFILT
SMP9210
2048 SAD
©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 •
www.summitmicro.com
Characteristics subject to change without notice
2048 3.3 10/03/01
1
SMP9210, SMP9211, SMP9212
Preliminary
INTRODUCTION
The SMP9210, -11, -12 trio are serial input, voltage
output, dual 10-Bit digital to analog converters. They can
operate from a single 2.7V to 5.5V supply. Internal
precision buffers swing rail-to-rail with an input reference
range from ground to the positive supply.
They integrate two 10-Bit DACs and their associated
circuits: an enhanced unity gain operational amplifier
output, a 10-Bit volatile data latch, a 10-bit nonvolatile
data register and an industry standard 2-wire serial
interface.
Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapter and Windows GUI software obtainable from
Summit Microelectronics.
RECOMMENDED OPERATING CONDITIONS
Temperature
Voltage
–40ºC to 85ºC.
2.7V to 5.5V
FUNCTIONAL BLOCK DIAGRAMS
Note: Pinouts for these three drawings reflect the 14 pin SOIC package.
VDD
13
4
VREFH2
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
6
VOUT2
A0
3
INTERFACE
& CONTROL
LOGIC
A1 2
A2
1
5 VREFL2
CONFIGURATION
REGISTER
11 VREFH1
SDA 14
SCL 12
NON-
VOLATILE
REGISTER
CS
8
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
9
VOUT1
SMP9210
10 VREFL1
7
GND
2048 BD10 2.2
2
2048 3.3 10/03/01
SUMMIT MICROELECTRONICS, Inc.
SMP9210, SMP9211, SMP9212
Preliminary
VDD
13
4
VREFH2
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
6
VOUT2
A0
3
INTERFACE
& CONTROL
LOGIC
A1 2
A2
1
5 VREFL2
CONFIGURATION
REGISTER
11 VREFH1
SDA 14
SCL 12
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
9
VOUT1
8
MUTE#
10 VREFL1
SMP9211
7
GND
2048 BD11 2.2
VDD
13
4
VREFH2
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
6
VOUT2
A0
3
INTERFACE
& CONTROL
LOGIC
A1 2
A2
1
5 VREFL2
CONFIGURATION
REGISTER
11 VREFH1
SDA 14
SCL 12
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
9
VOUT1
VREF 8
PRECISION
REFERENCE
10 VREFL1
SMP9212
7
GND
2048 BD12 3.0
SUMMIT MICROELECTRONICS, Inc.
2048 3.3 10/03/01
3
SMP9210, SMP9211, SMP9212
Preliminary
PIN CONFIGURATIONS
14-Pin SOIC
SMP9210
A2
A1
A0
V
REF
H2
V
REF
L2
V
OUT
2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SDA
V
DD
SCL
V
REF
H1
V
REF
L1
V
OUT
1
CS
A2
A1
A0
V
REF
H2
V
REF
L2
V
OUT
2
GND
SMP9211
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SDA
V
DD
SCL
V
REF
H1
V
REF
L1
V
OUT
1
MUTE#
A2
A1
A0
V
REF
H2
V
REF
L2
V
OUT
2
GND
SMP9212
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SDA
V
DD
SCL
V
REF
H1
V
REF
L1
V
OUT
1
V
REF
2048 14-PCon
16-Pin SSOP
SMP9210
A2
NC
A1
A0
V
REF
H2
V
REF
L2
V
OUT
2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDA
NC
V
DD
SCL
V
REF
H1
V
REF
L1
V
OUT
1
CS
A2
NC
A1
A0
V
REF
H2
V
REF
L2
V
OUT
2
GND
SMP9211
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDA
NC
V
DD
SCL
V
REF
H1
V
REF
L1
V
OUT
1
MUTE#
A2
NC
A1
A0
V
REF
H2
V
REF
L2
V
OUT
2
GND
SMP9212
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDA
NC
V
DD
SCL
V
REF
H1
V
REF
L1
V
OUT
1
V
REF
2048 16-PCon
PIN DESCRIPTIONS
V
DD
Power supply input.
GND
Power supply return.
V
OUT
1
,
V
OUT
2
The voltage output of the DACs. It is buffered by a unity-
gain follower that can slew up to 1V/µs.
V
REF
L1, V
REF
L2
The lower of the voltage reference inputs. V
REF
L must be
equal to or greater than ground and less than V
REF
H.
V
REF
H1, V
REF
H2
The higher of the voltage reference inputs. V
REF
H must be
equal to or less than V
CC
and greater than V
REF
L.
A0, A1, A2
The address inputs for the serial interface logic. Bias-
ing the address inputs will determine the device’s bus
address that is contained within the serial data stream
when communicating over the serial bus.
SCL
The serial interface clock. It is used to clock the data in and
out. When writing to the device data must remain stable
while SCL is high. When reading from the device data is
clocked out on the falling edge of SCL.
SDA
The bidirectional pin used to transfer data in and out of
the device.
CS
Chip Select input (V
IH
= selected) in the 9210. See the
Block Diagrams.
MUTE#
Mute input (V
IL
= mute) in the 9211. See the Block
Diagrams.
V
REF
V
REF
output (1.25V) in the 9212. See the Block Diagrams.
Note: NC pins are not connected.
4
2048 3.3 10/03/01
SUMMIT MICROELECTRONICS, Inc.
SMP9210, SMP9211, SMP9212
Preliminary
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...................... –55°C to 125°C
Storage Temperature ........................... –65°C to 150°C
Lead Solder Temperature (10 secs) .................. 300 °C
Terminal Voltage with Respect to GND:
V
DD
................................ –0.3V to 6.0V
All Others ...................... –0.3V to 6.0V
θJ
A
.................. 14 Pin = 88, 16 pin = 115
θJ
C
.................. 14 Pin = 37, 16 pin = 40
*Comment
Stresses listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
DC OPERATING CHARACTERISTICS
(Over
Recommended Operating Conditions; Voltages are relative to GND)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Static Performance (1)
N
INL
DNL
VZSE
VFS
TCV
Resolution
Relative Accuracy
Differential nonlinearity
Zero scale error
Full scale voltage
Full scale temperature
coefficient
Offset error
Gain error
Matching Performance
Linearity matching error
Analog Output
I
OUT
LDREG
C
L
V
REF
H
V
REF
L
V
REF
OUT
(1) V
REF
L = 0.5V, V
REF
H = 4.5V
10
–2
Guaranteed monotonic
Data = 000
HEX
Data = 3FF
HEX
±15
–0.3
–0.5
0.3
0.5
–1
0
±1
±0.5
2
1
20
V
REF
H
–1LSB
Bits
LSB
LSB
mV
V
ppm
%VFS
%
±5
Data = 200
HEX
,
∆V
OUT
,
3LSB
Data = 200
HEX
, RL = 1k
Ω
to
∞
No oscillation
1
500
LSB
Output current
Load regulation @ halfscale
Capacitive load
Reference Voltages
±5
4
mA
LSB
pF
V
REF
H > V
REF
L
V
REF
L < V
REF
H
SMP9212
GND
1.25
V
DD
V
V
V
2048 Elect TableA 3.1
SUMMIT MICROELECTRONICS, Inc.
2048 3.3 10/03/01
5
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