512MB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
DDR3 SDRAM SODIMM
MT4JTF6464HY – 512MB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as per
component data sheet
• 204-pin, small outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 512MB (64 Meg x 64)
• V
DD
= V
DD
Q = 1.5V ±0.075V
• V
DDSPD
= +3.0V to +3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• 8 internal device banks for concurrent operation
• Fixed burst length (BL) of 8 and burst chop (BC)of
4 via the mode register set
• Adjustable data-output drive strength
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Pb-free
• Fly-by topology
• Terminated command, address, and control bus
Figure 1:
204-Pin SODIMM (MO-268 R/C C)
PCB height: 30.0mm (1.18in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Frequency/CAS latency
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.5ns @ CL = 10 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ C L = 8 (DDR3-1066)
–
2.5ns @ CL = 5 (DDR3-800)
–
2.5ns @ CL = 6 (DDR3-800)
1
Marking
None
I
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
Table 1:
Speed
Grade
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 10 CL = 9
–
1333
–
–
–
–
1333
1066
–
–
–
–
CL = 8
1066
800
–
1066
–
–
CL = 7
800
–
1066
800
–
–
CL = 6
–
–
800
–
–
800
CL = 5
–
–
–
–
800
–
t
RCD
(ns)
RP
(ns)
13.5
15
13.125
15
12.5
15
t
RC
(ns)
49.5
51
50.625
52.5
50
52.5
t
13.5
15
13.125
15
12.5
15
PDF: 09005aef82b2f090/Source: 09005aef82b2f012
JSF4C64_64x64HY.fm - Rev. A 7/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 5:
Symbol
A0–A12
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0–BA2) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE command.
Referenced to V
REF
CA. When enabled in the mode register (MR), A12 is sampled during READ/
WRITE commands to determine whether burst chop (on-the-fly) will be performed. (HIGH = BL8
or no burst chop, LOW = BC4 burst chop).
Bank address inputs:
BA0–BA2 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0–BA2 define which mode register, including MR,
EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
circuitry on the DDR3 SDRAM.
Data input mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with that input data, during a write access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and
DQS pins.
On-die termination:
ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS# and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being entered.
BA0–BA2
Input
CK0, CK0#
Input
CKE0
DM0–DM7
Input
Input
ODT0
Input
Input
Reset:
An active LOW CMOS input referenced to V
SS
and not referenced to V
REF
CA or V
REF
DQ.
(LVCMOS) The reset pin input receiver is a CMOS input and is defined as a rail-to-rail signal with a
DC HIGH
≥
0.8 × V
DD
Q and DC LOW
≤
0.2 × V
DD
Q (1.20V for HIGH and 0.30V for LOW). RESET#
assertion and desertion are asynchronous. System applications will most likely be
unterminated, heavily loaded, and have very slow slew rates. A slow slew rate receiver design is
recommended along with implementing on-chip noise filtering to prevent false triggering
(RESET# assertion minimum pulse width is 100ns).
SA0, SA1
Input
Presence-detect address inputs:
These pins are used to configure the presence-detect
device.
SCL
Input
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect data
transfer to and from the module.
S0#
Input
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
EVENT#
Output Temperature alarm output.
DQS0–DQS7
I/O
Data strobe:
Output with read data, input with write data for source synchronous operation.
DQS0#–DQS7#
Edge-aligned with read data, center-aligned with write data.
DQ0–DQ63
I/O
Data input/output:
Bidirectional data bus.
SDA
I/O
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and data
into and out of the presence-detect portion of the module.
Supply
Power supply:
1.5V ±0.075V.
V
DD
Supply
Reference voltage:
DQ, DM. V
DD
/2.
V
REF
DQ
Supply
Reference voltage:
Command, address, and control. V
DD
/2.
V
REF
CA
Supply
Termination voltage:
Used for address, command, control, and clock nets. V
DD
/2.
V
TT
Supply
Ground.
V
SS
Supply
Serial EEPROM power supply:
+3.0V to +3.6V.
V
DDSPD
NC
–
No connect:
These pins should be left unconnected.
PDF: 09005aef82b2f090/Source: 09005aef82b2f012
JSF4C64_64x64HY.fm - Rev. A 7/07 EN
RAS#, CAS#,
WE#
RESET#
Input
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
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