1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
DDR3 SDRAM SODIMM
MT8JSF12864H – 1GB
MT8JSF25664H – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as per
the component data sheet
• 204-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 1GB (128 Meg x 64) and 2GB (256 Meg x 64)
• V
DD
= 1.5V ±0.075V
• V
DDSPD
= +3.0V to +3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Pb-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
204-Pin SODIMM (MO-268 R/C B)
PCB height: 30.0mm (1.18in)
Options
•
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
204-pin DIMM
• Frequency/CAS latency
–
1.5ns @ CL = 8 (DDR3-1333)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.5ns @ CL = 10 (DDR3-1333)
2
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
2
–
2.5ns @ CL = 5 (DDR3-800)
2
–
2.5ns @ CL = 6 (DDR3-800)
2
Operating temperature
1
Marking
None
I
Y
-1G5
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Speed
Grade
-1G5
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 10
1333
1333
1333
–
–
–
–
CL = 9
1333
1333
–
–
–
–
–
CL = 8
1333
1066
1066
1066
1066
–
–
CL = 7
1066
1066
–
1066
–
–
–
CL = 6
800
800
800
800
800
800
800
CL = 5
800
–
–
–
–
800
–
t
RCD
t
RP
t
RC
(ns)
12
13.5
15
13.125
15
12.5
15
(ns)
12
13.5
15
13.125
15
12.5
15
(ns)
48
49.5
51
50.625
52.5
50
52.5
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. B 3/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
1GB
8K
16K (A[13:0])
8 (BA[2:0])
1Gb (128 Meg x 8)
1K (A[9:0])
1 (S0#)
2GB
8K
32K (A[14:0])
8 (BA[2:0])
2Gb (256 Meg x 8)
1K (A[9:0])
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
10.6 GB/s
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
8-8-8
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
MT8JSF12864H(I)Y-1G5__
MT8JSF12864H(I)Y-1G4__
MT8JSF12864H(I)Y-1G3__
MT8JSF12864H(I)Y-1G1__
MT8JSF12864H(I)Y-1G0__
MT8JSF12864H(I)Y-80C__
MT8JSF12864H(I)Y-80B__
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
2GB
Module
Bandwidth
10.6 GB/s
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
8-8-8
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
MT8JSF25664H(I)Y-1G5__
MT8JSF25664H(I)Y-1G4__
MT8JSF25664H(I)Y-1G3__
MT8JSF25664H(I)Y-1G1__
MT8JSF25664H(I)Y-1G0__
MT8JSF25664H(I)Y-80C__
MT8JSF25664H(I)Y-80B__
Notes:
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
1. The data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT8JSF12864HY-1G1B1.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. B 3/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
204-Pin DDR3 SODIMM Front
204-Pin DDR3 SODIMM Back
Symbol
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
EVENT#
SDA
SCL
V
TT
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
V
REF
DQ 53
55
V
SS
DQ0
57
DQ1
59
61
V
SS
DM0
63
V
SS
65
DQ2
67
DQ3
69
V
SS
71
DQ8
73
DQ9
75
V
SS
77
DQS1# 79
DQS1
81
V
SS
83
DQ10
85
DQ11
87
V
SS
89
DQ16
91
DQ17
93
V
SS
95
DQS2# 97
DQS2
99
V
SS
101
DQ18 103
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
CK0#
Notes:
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
A13
NC
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
V
SS
54
V
SS
DQ4
56
DQ28
DQ5
58
DQ29
V
SS
60
V
SS
DQS0# 62
DQ3#
DQS0
64
DQ3
V
SS
66
V
SS
DQ6
68
DQ30
DQ7
70
DQ31
V
SS
72
V
SS
DQ12
74
NC
DQ13
76
V
DD
V
SS
78
NC
1
NF/A14
DM1
80
RESET# 82
V
DD
V
SS
84
A11
DQ14
86
A7
DQ15
88
V
DD
V
SS
90
A6
DQ20
92
A4
DQ21
94
V
DD
V
SS
96
A2
DM2
98
A0
V
SS
100
V
DD
DQ22 102
CK1
DQ23 104 CK1#
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
V
DD
BA1
RAS#
V
DD
S0#
ODT0
V
DD
NC
NC
V
DD
V
REF
CA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1. Pin 80 is NF for 1GB and A14 for 2GB.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. B 3/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[14:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
.
A[13:0] address the 1Gb DDR3 devices and A[14:0] address the 2Gb
DDR3 devices.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DD
Q and DC LOW
≤
0.2 × V
DD
Q. RESET# assertion and deassertion are asynchronous. System applications will
most likely be unterminated, heavily loaded, and have very slow slew rates. A slow slew
rate receiver design is recommended along with implementing on-chip noise filtering to
prevent false triggering (RESET# assertion minimum pulse width is 100ns).
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize the
communication to and from the temperature sensor/SPD EEPROM.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply:
1.5V ±0.075V. The component V
DD
and V
DD
Q are connected to the module
V
DD
.
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Reference voltage:
Control, command, and address (V
DD
/2).
Reference voltage:
DQ, DM (V
DD
/2).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
BA[2:0]
Input
CK0, CK0#
Input
CKE0
DM[7:0]
Input
Input
ODT0
Input
RAS#, CAS#,
WE#
RESET#
Input
Input
(LVCMOS)
S0#
SA[1:0]
SCL
DQ[63:0]
DQS[7:0],
DQS#[7:0]
SDA
EVENT#
V
DD
V
DDSPD
V
REF
CA
V
REF
DQ
Input
Input
Input
I/O
I/O
I/O
Output
(open drain)
Supply
Supply
Supply
Supply
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. B 3/08 EN
4
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 6:
Symbol
V
SS
V
TT
NF
NC
Pin Descriptions (continued)
Type
Supply
Supply
–
–
Description
Ground.
Termination voltage:
Used for control, command, and address (V
DD
/2).
No function:
Connected within the module but provides no functionality.
No connect:
These pins are not connected on the module.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. B 3/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
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