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MT46V32M4TG-75: 产品描述DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66; 产品类别存储存储; 文件大小6MB，共81页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/

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MT46V32M4TG-75概述

DDR DRAM, 32MX4, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP-66

MT46V32M4TG-75规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Micron Technology
零件包装代码	TSOP
包装说明	0.400 INCH, PLASTIC, TSOP-66
针数	66
Reach Compliance Code	not_compliant
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	0.75 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
交错的突发长度	2,4,8
JESD-30 代码	R-PDSO-G66
JESD-609代码	e0
长度	22.22 mm
内存密度	134217728 bit
内存集成电路类型	DDR DRAM
内存宽度	4
功能数量	1
端口数量	1
端子数量	66
字数	33554432 words
字数代码	32000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	32MX4
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装等效代码	TSSOP66,.46
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	235
电源	2.5 V
认证状态	Not Qualified
刷新周期	4096
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	2,4,8
最大待机电流	0.003 A
最大压摆率	0.325 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	10.16 mm

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128Mb: x4, x8, x16 DDR SDRAM

Features

Double Data Rate (DDR) SDRAM

MT46V32M4 – 8 Meg x 4 x 4 Banks

MT46V16M8 – 4 Meg x 8 x 4 Banks

MT46V8M16 – 2 Meg x 16 x 4 Banks

Features

• V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V

• V

= +2.6V ±0.1V, V

Q = +2.6V ±0.1V (DDR400)

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture (x16 has two – one per byte)

• Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

(x16 has two – one per byte)

• Programmable burst lengths: 2, 4, or 8

• Auto refresh and self refresh modes

• Longer lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2 compatible)

• Concurrent auto precharge option is supported

•

RAS lockout supported (

RAP =

RCD)

Options

• Configuration

–

32 Meg x 4 (8 Meg x 4 x 4 banks)

–

16 Meg x 8 (4 Meg x 8 x 4 banks)

–

8 Meg x 16 (2 Meg x 16 x 4 banks)

• Plastic package – OCPL

–

66-pin TSOP

–

66-pin TSOP (Pb-free)

• Timing – cycle time

–

5ns @ CL = 3 (DDR400)

–

6ns @ CL = 2.5 (DDR333)

(TSOP only)

–

7.5ns @ CL = 2 (DDR266)

–

7.5ns @ CL = 2 (DDR266A)

–

7.5ns @ CL = 2.5 (DDR266B)

• Self refresh

–

Standard

–

Low-power self refresh

• Temperature rating

–

Commercial (0°C to 70°C)

–

Industrial (–40°C to +85°C)

• Revision

Marking

32M4

16M8

8M16

-5B

-6T

-75E

-75Z

-75

None

Notes: 1. Not recommended for new designs

Table 1:

Key Timing Parameters

CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and

CL = 3 (-5B)

Clock Rate (MHz)

Speed Grade

-5B

-6T

-75E/-75Z

-75

CL = 2

133

100

CL = 2.5

167

133

CL = 3

200

n/a

Data Out

Window

1.6ns

2.0ns

2.5ns

Access

Window

±0.70ns

±0.75ns

DQS–DQ

Skew

+0.40ns

+0.45ns

+0.50ns

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

128Mb_DDR_x4x8x16_D1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 DDR SDRAM

Table of Contents

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical Specifications – I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

BURST TERMINATE (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

POWER-DOWN (CKE Not Active). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

128Mb_DDRTOC.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 DDR SDRAM

Functional Description

The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is essentially a 2n-prefetch architecture with an inter-

face designed to transfer two data words per clock cycle at the I/O pins. A single read or

write access for the DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-

cycle data transfer at the internal DRAM core and two corresponding

n-bit

wide, one-

half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in

data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during

READs and by the memory controller during WRITEs. DQS is edge-aligned with data for

READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,

one for the lower byte and one for the upper byte.

The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a

selected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which may then

be followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVE command are used to select the bank and row to be accessed. The address

bits registered coincident with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8

locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs

allows for concurrent operation, thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. All

inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs

are SSTL_2, Class II compatible.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated

otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper

byte. For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS. For

the upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.

• Complete functionality is described throughout the document and any page or

diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

PDF: 09005aef816fd013/Source: 09005aef82a95a3a

DDR_x4x8x16_Core1.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT46V32M4TG-75

MT46V32M4TG-75概述

MT46V32M4TG-75规格参数

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