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ICS951601
Preliminary Product Preview
Pin Descriptions
Pin number
1
2, 13, 18, 21, 26,
33, 38, 46
3
4
9, 44
10, 30, 36, 42
5, 14, 17, 22, 27,
32, 39, 47
6
7
8, 43
24, 23, 20, 19,
16, 15, 12, 11,
29, 28, 25
35, 34, 31
41, 40, 37
45
48
Pin name
REF0
VDD
X1
X2
VDDA
SELxx
GND
SDATA
SCLK
GNDA
PCI1A (7:0)
PCI1B (2:0)
PCI2A (2:0)
PCI2B (2:0)
SPREAD
48MHz
Type
OUT
PWR
IN
OUT
PWR
IN
PWR
I/O
IN
PWR
OUT
OUT
OUT
OUT
IN
OUT
Description
Reference output
3.3V Power supply
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Analog 3.3V Power supply
Real time PCI output frequency selection pins
Ground pins
Data pin for I
2
C circuitry 5V tolerant
Clock input of I C input
Analog ground pins
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
Enables Spread Spectrum, default is on.
Fixed 48MHz clock output for USB.
2
0663C—10/04/05
2
ICS951601
Preliminary Prouct Preview
The information in this section assumes familiarity with I
2
C programming.
General I
2
C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends a dummy command code
• ICS clock will
acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will
acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will
acknowledge
each byte
one at a
time
.
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the
byte count
• Controller (host) acknowledges
• ICS clock sends first byte
(Byte 0) through byte
5
• Controller (host) will need to acknowledge each
byte
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above
must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is
issued.
At power-on, all registers are set to a default condition, as shown.
6.
0663C—10/04/05
3
ICS951601
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit2 Bit7 Bit6 Bit5 Bit4 66MHZ 33MHz
FEATURES
FS4 FS3 FS2 FS1 FS0
66
33
-0.25 % down spread
0
0
0
0
0
66
33
-0.5 % down spread
0
0
0
0
1
66
33
-1.0 % down spread
0
0
0
1
0
66
33
-1.5 % down spread
0
0
0
1
1
66
33
+ 0.25 % center spread
0
0
1
0
0
66
33
+0.5 % center spread
0
0
1
0
1
66
33
+ 1.0 % center spread
0
0
1
1
0
66.6
33.3
+1.5 % center spread
0
0
1
1
1
67.32
33.66
2% over-clocking
0
1
0
0
0
68.64
34.32
4% over-clocking
0
1
0
0
1
69.96
34.98
6% over-clocking
0
1
0
1
0
72.6
36.3
10% over-clocking
Bit
0
1
0
1
1
2,7:4 0
65.27
32.63
2% under- clocking
1
1
0
0
63.96
31.97
2% under- clocking
0
1
1
0
1
62.6
31.3
2% under- clocking
0
1
1
1
0
60
30
2% under- clocking
0
1
1
1
1
66.6
33.3
-1.4 % down spread
1
0
0
0
0
66.6
33.3
-1.6 % down spread
1
0
0
0
1
66.6
33.3
-1.8 % down spread
1
0
0
1
0
66.6
33.3
-2.0 % down spread
1
0
0
1
1
66.6
33.3
+ 1.4 % center spread
1
0
1
0
0
66.6
33.3
+ 1.6 % center spread
1
0
1
0
1
66.6
33.3
+ 1.8 % center spread
1
0
1
1
0
66.6
33.3
+ 2.0 % center spread
1
0
1
1
1
0-Frequency and Spread is seleced by hardware select. Latched input
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