NOT RECOMMENDED FOR NEW DESIGNS
4, 8 MEG x 36
ECC-OPTIMIZED DRAM SIMMs
DRAM
MODULE
FEATURES
• Four-CAS#, ECC-optimized configuration in a 72-
pin, single in-line memory module (SIMM)
• 16MB (4 Meg x 36) and 32MB (8 Meg x 36)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• 2,048-cycle refresh distributed across 32ms
• FAST PAGE MODE (FPM) access
MT9D436
MT18D836
For the latest data sheet revisions, please refer to the
Micron Web site:
www.micron.com/datasheets
PIN ASSIGNMENT (Front View)
72-Pin SIMM
1
36
37
72
OPTIONS
• Timing
60ns access
• Packages
72-pin SIMM
72-pin SIMM (Gold)
MARKING
-6
M
G
KEY TIMING PARAMETERS
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
60ns
35ns
30ns
15ns
40ns
PART NUMBERS
PART NUMBER
MT9D436M-x
MT9D436G-x
MT18D836M-x
MT18D836G-x
x = speed
CONFIGURATION
4 Meg x 36
4 Meg x 36
8 Meg x 36
8 Meg x 36
FEATURES
4 CAS#, ECC
4 CAS#, ECC
4 CAS#, ECC
4 CAS#, ECC
MODE
FPM
FPM
FPM
FPM
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
V
SS
19
A10
37
DQ18
55
DQ13
2
DQ1
20
DQ5
38
DQ36
56
DQ31
3
DQ19
21
DQ23
39
V
SS
57
DQ14
4
DQ2
22
DQ6
40
CAS0#
58
DQ32
5
DQ20
23
DQ24
41
CAS2#
59
V
DD
6
DQ3
24
DQ7
42
CAS3#
60
DQ33
7
DQ21
25
DQ25
43
CAS1#
61
DQ15
8
DQ4
26
DQ8
44
RAS0#
62
DQ34
9
DQ22
27
DQ26
45 NC/RAS1#* 63
DQ16
10
V
DD
28
A7
46
NC
64
DQ35
11
NC
29 NC (A11) 47
WE#
65
DQ17
12
A0
30
V
DD
48
NC
66
NC
13
A1
31
A8
49
DQ10
67
PRD1
14
A2
32
A9
50
DQ28
68
PRD2
15
A3
33 NC/RAS3#* 51
DQ11
69
PRD3
16
A4
34
RAS2#
52
DQ29
70
PRD4
17
A5
35
DQ27
53
DQ12
71
NC
18
A6
36
DQ9
54
DQ30
72
V
SS
*32MB version only
NOTE:
Symbols in parentheses are not used on these
modules but may be used for other modules in
this product family. They are for reference only.
GENERAL DESCRIPTION
The MT9D436 and MT18D836 are randomly
accessed, 16MB and 32MB solid-state memories orga-
nized in a x36 configuration. These modules are de-
signed for systems that utilize ECC and do not conduct
single-byte accesses. These modules do not support
parity functionality.
During READ or WRITE cycles, each bit is uniquely
addressed through 20 address bits that are entered 10
bits (A0-A9) at a time. RAS# is used to latch the first 10
bits and CAS#, the latter 10 bits. READ or WRITE cycles
are selected with the WE# input. A logic HIGH on WE#
dictates read mode, while a logic LOW on WE# dictates
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM84_2.p65 – Rev. 9/98
write mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE# or CAS#, whichever occurs
last. EARLY WRITE occurs when WE# goes LOW prior to
CAS# going LOW, and the output pin(s) remain open
(High-Z) until the next CAS# cycle.
PAGE MODE
Page operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-ad-
dress-defined page boundary. The page cycle is al-
ways initiated with a row address strobed in by RAS#,
followed by a column address strobed in by CAS#. Ad-
ditional columns may be accessed by providing valid
column addresses, strobing CAS# and holding RAS#
LOW, thus executing faster memory cycles. Returning
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
NOT RECOMMENDED FOR NEW DESIGNS
4, 8 MEG x 36
ECC-OPTIMIZED DRAM SIMMs
PAGE MODE (continued)
RAS# HIGH terminates page mode operation, i.e., closes
the page.
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining
power and executing anyRAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so
that all 2,048 combinations of RAS# addresses are ex-
ecuted at least every 32ms, regardless of sequence.
The CBR REFRESH cycle will invoke the refresh counter
for automatic RAS# addressing.
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
JEDEC-DEFINED
PRESENCE-DETECT – MT9D436 (16MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PIN
67
68
69
70
-6
Vss
NC
NC
NC
JEDEC-DEFINED
PRESENCE-DETECT – MT18D836 (32MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PIN
67
68
69
70
-6
NC
Vss
NC
NC
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM84_2.p65 – Rev. 9/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
NOT RECOMMENDED FOR NEW DESIGNS
4, 8 MEG x 36
ECC-OPTIMIZED DRAM SIMMs
FUNCTIONAL BLOCK DIAGRAM
MT9D436 (16MB)
DQ1
DQ8
DQ9, 18, 27, 36
DQ10
DQ17
DQ1 - 4
WE#
U1
CAS0#
RAS0#
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U2
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U5
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U3
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U4
CAS#
RAS#
OE# A0–A10
CAS1#
WE#
11
11
11
11
11
DQ19
DQ26
DQ28
DQ35
DQ1 - 4
WE#
U6
CAS2#
RAS2#
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U7
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U8
U3
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U9
CAS#
RAS#
OE# A0–A10
CAS3#
A0–A10
11
11
11
11
V
DD
V
SS
U1-U9
U1-U9
U1-U9 = 4 Meg x 4 DRAMs
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM84_2.p65 – Rev. 9/98
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
NOT RECOMMENDED FOR NEW DESIGNS
4, 8 MEG x 36
ECC-OPTIMIZED DRAM SIMMs
FUNCTIONAL BLOCK DIAGRAM
MT18D836 (32MB)
DQ1
DQ8
DQ9, 18, 27, 36
DQ10
DQ17
DQ1 - 4
WE#
U1
CAS0#
RAS0#
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U2
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U5
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U3
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U4
CAS#
RAS#
OE# A0–A10
CAS1#
WE#
11
11
11
11
11
DQ19
DQ26
DQ28
DQ35
DQ1 - 4
WE#
U6
CAS2#
RAS2#
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U7
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U8
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U9
CAS#
RAS#
OE# A0–A10
CAS3#
A0–A10
11
11
11
11
DQ1
DQ8
DQ9, 18, 27, 36
DQ10
DQ17
DQ1 - 4
WE#
U10
CAS#
RAS1#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U11
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U14
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U12
CAS#
RAS#
OE# A0–A10
DQ1 - 4
WE#
U13
CAS#
RAS#
OE# A0–A10
11
11
11
11
11
DQ19
DQ26
DQ28
DQ35
DQ1 - 4
WE#
CAS#
RAS3#
RAS#
OE# A0–A10
U15
DQ1 - 4
WE#
CAS#
RAS#
OE# A0–A10
U16
DQ1 - 4
WE#
CAS#
RAS#
OE# A0–A10
U17
DQ1 - 4
WE#
CAS#
RAS#
OE# A0–A10
U18
11
11
11
11
V
DD
V
SS
U1-U18
U1-U18
U1-U18 = 4 Meg x 4 DRAMs
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM84_2.p65 – Rev. 9/98
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
NOT RECOMMENDED FOR NEW DESIGNS
4, 8 MEG x 36
ECC-OPTIMIZED DRAM SIMMs
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply Relative to V
SS
........... -1V to +7V
Operating Temperature, T
A
(ambient) ... 0ºC to +70ºC
Storage Temperature (plastic) ............ -55ºC to +125ºC
Power Dissipation ........................................................ 9W
Short Circuit Output Current ................................. 50mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6) (V
DD
= +5V ±10%)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
INPUT LEAKAGE CURRENT:
Any input 0V
≤
V
IN
≤
5.5V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT:
(DQ is disabled; 0V
≤
V
OUT
≤
5.5V)
OUTPUT LEVELS:
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
CAS0#-CAS3#
A0-A10, WE#
RAS0#-RAS3#
DQ1-DQ36
SYMBOL MIN
V
DD
V
IH
V
IL
I
I
1
I
I
2
I
I
3
I
OZ
V
OH
V
OL
4.5
2.4
-1.0
-12
-36
-10
-10
2.4
–
MAX UNITS NOTES
5.5
V
DD
+1
0.8
12
36
10
10
–
0.4
V
V
V
µA
µA
µA
µA
V
V
22
22
22
Icc SPECIFICATIONS AND CONDITIONS
(Notes: 1, 5, 6) (V
DD
= +5V ±10%)
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: (CMOS)
(RAS# = CAS# = Other Inputs = V
DD
- 0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
SYMBOL SIZE
I
CC
1
I
CC
2
16MB
32MB
16MB
32MB
16MB
32MB
16MB
32MB
16MB
32MB
16MB
32MB
MAX
-6
18
36
5
9
1,170
1,188
900
918
1,170
1,188
1,170
1,188
UNITS NOTES
mA
mA
mA
3, 21
I
CC
3
I
CC
4
mA
3, 21
I
CC
5
mA
3, 21
I
CC
6
mA
3, 4
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM84_2.p65 – Rev. 9/98
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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