2Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J512M4 – 64 Meg x 4 x 8 Banks
MT41J256M8 – 32 Meg x 8 x 8 Banks
MT41J128M16 – 16 Meg x 16 x 8 Banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= +1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
CAS READ latency (CL): 5, 6, 7, 8, 9, 10, or 11
POSTED CAS ADDITIVE latency (AL): 0, CL - 1,
CL - 2
CAS WRITE latency (CWL): 5, 6, 7, 8, based on
t
CK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0°C to +95°C
–
64ms, 8192 cycle refresh at 0°C to +85°C
–
32ms, 8192 cycle refresh at +85°C to +95°C
Clock frequency range of 300–800 MHz
Self refresh temperature (SRT)
Write leveling
Multipurpose register
Output driver calibration
Options
1
•
Configuration
–
512 Meg x 4
–
256 Meg x 8
–
128 Meg x 16
•
FBGA package (Pb-free) – x4, x8
–
78-ball (8mm x 10.5mm) Rev. H
–
78-ball (9mm x 11.5mm) Rev. D
–
82-ball (12.5mm x 15mm) Rev. A
•
FBGA package (Pb-free) – x16
–
96-ball (9mm x 14mm) Rev. D
•
Timing – cycle time
–
1.07ns @ CL = 13 (DDR3-1866)
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 10 (DDR3-1333)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 8 (DDR3-1066)
–
1.87ns @ CL = 7 (DDR3-1066)
•
Operating temperature
–
Commercial (0°C
≤
T
C
≤
+95°C)
–
Industrial (–40°C
≤
T
C
≤
+95°C)
•
Revision
Note:
Marking
512M4
256M8
128M16
DA
HX
JE
HA
-107
-125
-15
-15E
-187
-187E
None
IT
:A/:D/:H
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2
-125
1, 2
-15
3
-15E
1
-187
-187E
Notes:
Data Rate (MT/s)
1866
1600
1333
1333
1066
1066
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
10-10-10
9-9-9
8-8-8
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
15
13.5
15
13.1
13.91
13.75
15
13.5
15
13.1
13.91
13.75
15
13.5
15
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1066, CL = 8 (-187).
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
512 Meg x 4
64 Meg x 4 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
2K (A[11, 9:0])
256 Meg x 8
32 Meg x 8 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
1K (A[9:0])
128 Meg x 16
16 Meg x 16 x 8 banks
8K
16K (A[13:0])
8 (BA[2:0])
1K (A[9:0])
Figure 1: DDR3 Part Numbers
Example Part Number: MT41J256M8JE-15:D
-
MT41J
Configuration
Package
Speed
:
Revision
{
:D
Configuration
512 Meg x 4
256 Meg x 8
128 Meg x 16
512M4
256M8
128M16
-107
JE
HX
DA
HA
-125
-15
-15E
-187
-187E
Speed Grade
tCK = 1.07ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 10
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 8
tCK = 1.87ns, CL = 7
Temperature
Commercial
Industrial temperature
None
IT
Revision
Package
82-ball 12.5mm x 15mm FBGA
78-ball 9mm x 11.5mm FBGA
78-ball 8mm x 10.5mm FBGA
96-ball 9mm x 14mm FBGA
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com
for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature .............................................................................................................................. 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ...................................................................................................................................... 25
Electrical Specifications .................................................................................................................................. 29
Absolute Ratings ........................................................................................................................................ 29
Input/Output Capacitance ......................................................................................................................... 30
Thermal Characteristics .................................................................................................................................. 31
Electrical Specifications – I
DD
Specifications and Conditions Definitions .......................................................... 32
Electrical Characteristics – I
DD
Specifications .................................................................................................. 43
Electrical Specifications – DC and AC .............................................................................................................. 48
DC Operating Conditions ........................................................................................................................... 48
Input Operating Conditions ........................................................................................................................ 48
AC Overshoot/Undershoot Specification ..................................................................................................... 51
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 54
Slew Rate Definitions for Differential Input Signals ...................................................................................... 56
ODT Characteristics ....................................................................................................................................... 57
ODT Resistors ............................................................................................................................................ 57
ODT Sensitivity .......................................................................................................................................... 59
ODT Timing Definitions ............................................................................................................................. 59
Output Driver Impedance ............................................................................................................................... 63
34 Ohm Output Driver Impedance .............................................................................................................. 64
34 Ohm Driver ............................................................................................................................................ 65
34 Ohm Output Driver Sensitivity ................................................................................................................ 66
Alternative 40 Ohm Driver .......................................................................................................................... 67
40 Ohm Output Driver Sensitivity ................................................................................................................ 67
Output Characteristics and Operating Conditions ........................................................................................... 69
Reference Output Load ............................................................................................................................... 71
Slew Rate Definitions for Single-Ended Output Signals ................................................................................ 72
Slew Rate Definitions for Differential Output Signals ................................................................................... 73
Speed Bin Tables ............................................................................................................................................ 74
Electrical Characteristics and AC Operating Conditions ................................................................................... 78
Command and Address Setup, Hold, and Derating .......................................................................................... 97
Data Setup, Hold, and Derating ..................................................................................................................... 105
Commands – Truth Tables ............................................................................................................................. 112
Commands ................................................................................................................................................... 115
DESELECT ................................................................................................................................................ 115
NO OPERATION ........................................................................................................................................ 115
ZQ CALIBRATION LONG ........................................................................................................................... 115
ZQ CALIBRATION SHORT ......................................................................................................................... 115
ACTIVATE ................................................................................................................................................. 115
READ ........................................................................................................................................................ 115
WRITE ...................................................................................................................................................... 116
PRECHARGE ............................................................................................................................................. 116
REFRESH .................................................................................................................................................. 117
SELF REFRESH .......................................................................................................................................... 118
DLL Disable Mode ..................................................................................................................................... 119
Contents
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Input Clock Frequency Change ...................................................................................................................... 123
Write Leveling ............................................................................................................................................... 125
Write Leveling Procedure ........................................................................................................................... 127
Write Leveling Mode Exit Procedure ........................................................................................................... 129
Initialization ................................................................................................................................................. 130
Mode Registers .............................................................................................................................................. 132
Mode Register 0 (MR0) .................................................................................................................................. 133
Burst Length ............................................................................................................................................. 133
Burst Type ................................................................................................................................................ 134
DLL RESET ................................................................................................................................................ 135
Write Recovery .......................................................................................................................................... 135
Precharge Power-Down (Precharge PD) ..................................................................................................... 136
CAS Latency (CL) ....................................................................................................................................... 136
Mode Register 1 (MR1) .................................................................................................................................. 137
DLL Enable/DLL Disable ........................................................................................................................... 137
Output Drive Strength ............................................................................................................................... 138
OUTPUT ENABLE/DISABLE ...................................................................................................................... 138
TDQS Enable ............................................................................................................................................. 138
On-Die Termination .................................................................................................................................. 139
WRITE LEVELING ..................................................................................................................................... 139
POSTED CAS ADDITIVE Latency ................................................................................................................ 139
Mode Register 2 (MR2) .................................................................................................................................. 141
CAS Write Latency (CWL) ........................................................................................................................... 141
AUTO SELF REFRESH (ASR) ...................................................................................................................... 142
SELF REFRESH TEMPERATURE (SRT) ....................................................................................................... 142
SRT vs. ASR ............................................................................................................................................... 143
DYNAMIC ODT ......................................................................................................................................... 143
Mode Register 3 (MR3) .................................................................................................................................. 144
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144
MPR Functional Description ...................................................................................................................... 145
MPR Register Address Definitions and Bursting Order ................................................................................ 146
MPR Read Predefined Pattern .................................................................................................................... 151
MODE REGISTER SET (MRS) Command ........................................................................................................ 151
ZQ CALIBRATION Operation ......................................................................................................................... 152
ACTIVATE Operation ..................................................................................................................................... 153
READ Operation ............................................................................................................................................ 155
WRITE Operation .......................................................................................................................................... 166
DQ Input Timing ....................................................................................................................................... 174
PRECHARGE Operation ................................................................................................................................. 176
SELF REFRESH Operation ............................................................................................................................. 176
Extended Temperature Usage ........................................................................................................................ 178
Power-Down Mode ....................................................................................................................................... 179
RESET Operation ........................................................................................................................................... 187
On-Die Termination (ODT) ........................................................................................................................... 189
Functional Representation of ODT ............................................................................................................. 189
Nominal ODT ........................................................................................................................................... 189
Dynamic ODT ............................................................................................................................................... 191
Functional Description .............................................................................................................................. 191
Synchronous ODT Mode ............................................................................................................................... 196
ODT Latency and Posted ODT ................................................................................................................... 196
Timing Parameters .................................................................................................................................... 196
ODT Off During READs .............................................................................................................................. 199
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Asynchronous ODT Mode .............................................................................................................................. 201
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) ................................................. 203
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ....................................................... 205
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ..................................................... 207
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
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