TECHNOLOGY, INC.
MT2LDT132H(X)(L), MT4LDT232H(X)(L)
1 MEG, 2 MEG x 32 DRAM MODULES
SMALL-OUTLINE
DRAM MODULE
FEATURES
• JEDEC- and industry-standard pinout in a 72-pin,
small-outline, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process.
• Single +3.3V
±0.3V
power supply
• All device pins are TTL-compatible
• Low power, 12mW standby; 506mW active, typical
(8MB)
• Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR)
and HIDDEN; optional Extended CBR
• 1,024-cycle refresh distributed across 16ms or
1,024-cycle extended refresh distributed across 128ms
• FAST PAGE MODE (FPM) operating mode or
Extended Data-Out (EDO) PAGE MODE operating
mode
• 5V-tolerant inputs and I/Os (5.5V maximum V
IH
level)
1 MEG, 2 MEG x 32
4, 8 MEGABYTE, 3.3V, OPTIONAL
EXTENDED REFRESH, FAST PAGE OR EDO
PAGE MODE
PIN ASSIGNMENT (Front View)
72-Pin Small-Outline DIMM
(DE-1) 1 Meg x 32
(DE-2) 2 Meg x 32
1
PIN # FRONT
PIN #
1
V
SS
2
3
DQ1
4
5
DQ3
6
7
DQ5
8
9
DQ7
10
11
PRD1
12
13
A1
14
15
A3
16
17
A5
18
19
NC
20
21
DQ8
22
23
DQ10
24
25
DQ12
26
27
DQ14
28
29
NC
30
31
A8
32
33 NC/?R
?
A
?
S
/
3* 34
35
DQ15
36
*8MB version only
BACK
DQ0
DQ2
DQ4
DQ6
V
CC
A0
A2
A4
A6
NC
DQ9
DQ11
DQ13
A7
V
CC
A9
?
R
?
A
?
S
/
2
NC
PIN # FRONT
PIN #
37
DQ16
38
39
V
SS
40
41
?
C
?
A
?
S
/
2
42
43
?
C
?
A
?
S
/
1
44
45 NC/?R
?
A
?
S
/
1* 46
47
?
WE
/
48
49
DQ18
50
51
DQ20
52
53
DQ22
54
55
NC
56
57
DQ25
58
59
DQ28
60
61
V
CC
62
63
DQ30
64
65
NC
66
67
PRD3
68
69
PRD5
70
71
PRD7
72
BACK
DQ17
?
C
?
A
?
S
/
0
?
C
?
A
?
S
/
3
?
R
?
A
?
S
/
0
NC
NC
DQ19
DQ21
DQ23
DQ24
DQ26
DQ27
DQ29
DQ31
PRD2
PRD4
PRD6
V
SS
OPTIONS
• Timing
60ns access
70ns access
• Packages
72 -pin Small-Outline DIMM (gold)
• Operating Modes
FAST PAGE MODE
EDO PAGE MODE
• Refresh
Standard/16ms
Extended Refresh/128ms
MARKING
-6
-7
G
Blank
X
Blank
L
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
12ns
12ns
FPM Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
MT2LDT132H(X)(L), MT4LDT232H(X)(L)
DM40.pm5 – Rev. 12/95
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
TECHNOLOGY, INC.
MT2LDT132H(X)(L), MT4LDT232H(X)(L)
1 MEG, 2 MEG x 32 DRAM MODULES
always initiated with a row-address strobed-in by
?
R
?
A
/
S
followed by a column-address strobed-in by
?
CA
/
S. C
?
A
/
S
?
?
may be toggled-in by holding
?
R
?
A
/
S LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning
?
R
?
A
/
S HIGH terminates the FAST PAGE
MODE operation.
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT2LDT132HG-xx X
MT2LDT132HG-xx XL
MT4LDT232HG-xx X
MT4LDT232HG-xx XL
DESCRIPTION
1 Meg x 32, EDO
1 Meg x 32, EDO, Extended Refresh
2 Meg x 32, EDO
2 Meg x 32, EDO, Extended Refresh
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after
?
C
?
A
/
S
goes back HIGH. EDO provides for
?
C
?
A
/
S precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of
?
C
?
A
/
S output control provides for pipeline
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
A
/
S. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid or become
valid after
?
C
?
A
/
S goes HIGH, as long as R
?
A
/
S and
?
O
?
E are held
?
LOW (reference MT4LC1M16E5 DRAM data sheet for
additional information on EDO functionality).
xx = speed
FPM Operating Mode
PART NUMBER
MT2LDT132HG-xx
MT2LDT132HG-xx L
MT4LDT232HG-xx
MT4LDT232HG-xx L
DESCRIPTION
1 Meg x 32
1 Meg x 32, Extended Refresh
2 Meg x 32
2 Meg x 32, Extended Refresh
xx = speed
GENERAL DESCRIPTION
The MT2LDT132H(X)(L) and MT4LDT232H(X)(L) are
randomly accessed 4MB and 8MB solid-state memories
organized in a small outline x32 configuration. They are
specially processed to operate from +3.0V to 3.6V for low
voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits which are entered 10
bits (A0 -A9) at a time.
?
R
?
A
/
S is used to latch the first 10 bits
and
?
C
?
A
/
S the latter 10 bits.
READ and WRITE cycles are selected with the
?
W
/
E input.
A logic HIGH on
?
W
/
E dictates READ mode while a logic
LOW on
?
W
/
E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of
?
W
/
E or
?
C
?
A
/
S,
whichever occurs last. If
?
W
/
E goes LOW prior to
?
C
?
A
/
S going
LOW, the output pin(s) remain open (High-Z) until the next
?
C
?
A
/
S cycle.
REFRESH
Memory cell data is retained in its correct state by main-
taining power and executing any
?
R
?
A
/
S cycle (READ, WRITE)
or
?
R
?
A
/
S refresh cycle (?RA
/
S ONLY, CBR or HIDDEN) so that
?
all combinations of
?
R
?
A
/
S addresses (A0 -A9) are executed at
least every
t
REF, regardless of sequence. The CBR RE-
FRESH cycle will invoke the internal refresh counter for
automatic
?
R
?
A
/
S addressing.
An optional Extended Refresh mode is also available on
the MT2LDT132H(X) L and MT4LDT232H(X) L. The “L”
version allows the user the choice of a dynamic refresh
mode at the extended refresh period of 128ms.
STANDBY
Returning
?
R
?
A
/
S and
?
C
?
A
/
S HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the
?
R
?
A
/
S HIGH time.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
(A0 -A9) page boundary. The FAST PAGE MODE cycle is
MT2LDT132H(X)(L), MT4LDT232H(X)(L)
DM40.pm5 – Rev. 12/95
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
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