8 MEG x 8
FPM DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 13 row, 10 column addresses (E1) or
12 row, 11 column addresses (B6)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
MT4LC8M8E1, MT4LC8M8B6
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/products/datasheets/dramds.html
PIN ASSIGNMENT (Top View)
32-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
32-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
SS
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
MARKING
B6
E1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
Vss
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
SS
**A12 on E1 version, NC on B6 version
DJ
TG
8 MEG x 8 FPM DRAM PART NUMBERS
PART NUMBER
REFRESH
ADDRESSING
8K
8K
8K
8K
4K
4K
4K
4K
PACKAGE REFRESH
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
-5
-6
None
S*
NOTE:
1. The 8 Meg x 8 FPM DRAM base number
differentiates the offerings in one place—
MT4LC8M8E1. The fifth field distinguishes
various options: E1 designates an 8K refresh and
B6 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC8M8E1DJ-x
MT4LC8M8E1DJ-x S
MT4LC8M8E1TG-x
MT4LC8M8E1TG-x S
MT4LC8M8B6DJ-x
MT4LC8M8B6DJ-x S
MT4LC8M8B6TG-x
MT4LC8M8B6TG-x S
x = speed
GENERAL DESCRIPTION
The 8 Meg x 8 DRAMs are high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits organized in a x8 configuration. The
8 Meg x 8 DRAMs are functionally organized as 8,388,608
locations containing eight bits each. The 8,388,608
memory locations are arranged in 8,192 rows by 1,024
columns for the MT4LC8M8E1 or 4,096 rows by 2,048
columns for the MT4LC8M8B6. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the
MT4LC8M8E1DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
FPM DRAM
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8E1 (13 row addresses)
WE#
CAS#
DATA-IN
BUFFER
8
DQ0-
DQ7
CONTROL
LOGIC
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
8
8
OE#
10
COLUMN-
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
10
COLUMN
DECODER
1,024
SENSE AMPLIFIERS
I/O GATING
1,024 x 8
8
A0-
A12
REFRESH
COUNTER
ROW SELECT
13
13
ROW-
ADDRESS
BUFFERS (13)
COMPLEMENT
SELECT
ROW
DECODER
13
8,192
8,192 x 8
8,192 x 1,024 x 8
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8B6 (12 row addresses)
WE#
CAS#
DATA-IN
BUFFER
8
DQ0-
DQ7
CONTROL
LOGIC
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
8
8
OE#
11
COLUMN-
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
11
COLUMN
DECODER
2,048
SENSE AMPLIFIERS
I/O GATING
2,048 x 8
8
A0-
A11
REFRESH
COUNTER
ROW SELECT
12
12
ROW-
ADDRESS
BUFFERS (12)
COMPLEMENT
SELECT
ROW
DECODER
12
4,096
4,096 x 8
4,096 x 2,048 x 8
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
FPM DRAM
GENERAL DESCRIPTION (continued)
RAS# signal, then the column address by CAS#. Both
devices provide FAST-PAGE-MODE operation, allow-
ing for fast successive data operations (READ, WRITE,
or READ-MODIFY-WRITE) within a given row.
The MT4LC8M8E1 and MT4LC8M8B6 must be re-
freshed periodically in order to retain stored data.
the MT4LC8M8B6 refreshes one row for every CBR
cycle. So with either device, executing 4,096 CBR cycles
covers all rows. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing. Alternatively, RAS#-ONLY REFRESH capability is
inherently provided. However, with this method only
one row is refreshed at a time; so for the MT4LC8M8E1,
8,192 RAS#-ONLY REFRESH cycles must be executed
every 64ms to cover all rows. Some compatibility issues
may become apparent. JEDEC strongly recommends
the use of CBR REFRESH for this device.
An optional self refresh mode is also available on the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified
t
RASS. The “S” option allows for
an extended refresh period of 128ms, or 31.25µs per
row for a 4K refresh and 15.625µs per row for an 8K
refresh when using a distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as
well as during a standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes RAS#-ONLY or burst CBR refresh se-
quence, all rows must be refreshed with a refresh rate of
t
RC minimum prior to the resumption of normal
operation.
FAST PAGE MODE ACCESS
Each location in the DRAM is uniquely addressable
as mentioned in the General Description. The data for
each location is accessed via the eight I/O pins (DQ0-
DQ7). The WE# signal must be activated to execute a
WRITE operation; otherwise, a READ operation will be
performed. The OE# signal must be activated to enable
the DQ output drivers for a read access and can be
deactivated to disable output data if necessary.
FAST-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the FAST-PAGE-MODE opera-
tion.
DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (E1)
or all 4,096 rows (B6) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC8M8E1 in-
ternally refreshes two rows for every CBR cycle, whereas
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Relative to V
SS
................ -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to V
SS
....................................... -1V to +4.6V
Operating Temperature, T
A
(ambient) ... 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6) (V
CC
= +3.3V ±0.3V)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at V
IN
(0V
£
V
IN
£
V
CC
+ 0.3V);
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
I
OUT
= -2mA
OUTPUT LOW VOLTAGE:
I
OUT
= 2mA
OUTPUT LEAKAGE CURRENT:
Any output at V
OUT
(0V
£
V
OUT
£
V
CC
+ 0.3V);
DQ is disabled and in High-Z state
SYMBOL
V
CC
V
IH
V
IL
I
I
MIN
3
2
-0.3
-2
MAX
3.6
V
CC
+ 0.3
0.8
2
UNITS NOTES
V
V
V
µA
26
26
V
OH
V
OL
I
OZ
2.4
–
-5
–
0.4
5
V
V
µA
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8 MEG x 8
FPM DRAM
I
CC
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) (V
CC
= +3.3V ±0.3V)
PARAMETER/CONDITION
STANDBY CURRENT: TTL
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: CMOS
(RAS# = CAS#
ž
V
CC
- 0.2V; DQs may be left open;
Other inputs: V
IN
•
V
CC
- 0.2V or V
IN
£
0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current (RAS# = V
IL
,
CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# =
t
RAS (MIN); WE# = V
CC
- 0.2V;
A0-A11, OE# and D
IN
= V
CC
- 0.2V or 0.2V
(D
IN
may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with
RAS#
•
t
RASS (MIN) and CAS# held LOW;
WE# = V
CC
- 0.2V; A0-A11, OE# and D
IN
=
V
CC
- 0.2V or 0.2V (D
IN
may be left open)
4K
SYMBOL SPEED REFRESH
I
CC
1
ALL
1
8K
REFRESH UNITS NOTES
1
mA
I
CC
2
I
CC
3
ALL
-5
-6
-5
-6
-5
-6
-5
-6
500
175
165
105
95
175
165
175
165
500
135
125
105
95
135
125
175
165
µA
mA
25
I
CC
4
mA
25
I
CC
5
mA
22
I
CC
6
mA
4, 7
I
CC
7
ALL
400
400
µA
4, 7
I
CC
8
ALL
400
400
µA
4, 7
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
