ADVANCE
‡
512Mb: x16
MOBILE SDRAM
MOBILE SDRAM
MT48V32M16LFFN, MT48V32M16LFBN,
MT48H32M16LFFN, MT48H32M16LFBN
8 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Deep Power Down
• Partial Array Self Refresh power-saving mode
BALL ASSIGNMENT (Top View)
54-Ball VFBGA
1
A
B
C
D
E
F
G
H
J
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
V
SS
2
DQ15
DQ13
DQ11
DQ9
NC
CK
A11
A7
A5
3
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
CKE
A9
A6
A4
4
5
6
7
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
CAS\
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS\
BA1
A1
A2
9
V
DD
DQ1
DQ3
DQ5
DQ7
WE\
CS\
A10
VDD
OPTIONS
• V
DD
/V
DD
Q
2.5V/2.5V–1.8V
1.8V/1.8V
• Configurations
32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic Packages
54-pinTSOP (400 mil)
1
54-pinTSOP (400 mil) Lead-Free
1
54-ball VFBGA (10mm x 12.5mm)
2
54-ball VFBGA (Lead Free)
2
• Timing (Cycle Time)
6.0ns @ CL=3 (167 MHz)
7.5ns @ CL = 3 (133 MHz)
8.0ns @ CL = 3 (125 MHz)
• Operating Temperature
Commercial (0
o
C to + 70
o
C)
Industrial (-40
o
C to + 85
o
C)
MARKING
V
H
32M16
TG
P
FN
BN
-6A
-75
-8
None
IT
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1,024(A0–A9)
KEY TIMING PARAMETERS
SPEED
GRADE
-6A
-75
-8
-75
-8
-8
CLOCK
FREQUENCY
167MHz
133MHz
125MHz
104MHz
104MHz
50MHz
ACCESS TIME
CL=1* CL=2* CL=3*
–
–
–
–
–
19ns
–
–
–
6ns
8ns
–
5.0ns
5.4ns
7ns
–
–
–
SETUP HOLD
TIME TIME
1.5ns
1.5ns
2.5ns
1.5ns
2.5ns
2.5ns
0.8ns
0.8ns
1.0ns
0.8ns
1.0ns
1.0ns
NOTE:
1. Contact Factory for availability.
2. Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part mark that is different
from the part number. See our Web site for more
information on abbreviated component marks at
http://www.micron.com/decoder.
*CL = CAS (READ) latency
09005aef80d053fa
MobileRamY27L_A.p65 – Pub. 07/03
‡
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
512Mb: x16
MOBILE SDRAM
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
V
DD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
x16
Vss
DQ15
VssQ
DQ14
DQ13
V
DD
Q
DQ12
DQ11
VssQ
DQ10
DQ9
V
DD
Q
DQ8
Vss
NC
DQMH
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
09005aef80d053fa
MobileRamY27L_A.p65 – Pub. 07/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
ADVANCE
512Mb: x16
MOBILE SDRAM
512Mb SDRAM PART NUMBERS
PART NUMBER
1
MT48V32M16LFFN-6A
MT48V32M16LFFN-75
MT48V32M16LFFN-8
MT48H32M16LFFN-6A
MT48H32M16LFFN-75
MT48H32M16LFFN-8
MT48V32M16LFTG-6A
MT48V32M16LFTG-75
MT48V32M16LFTG-8
MT48H32M16LFTG-6A
MT48H32M16LFTG-75
MT48H32M16LFTG-8
V
DD
/V
DD
Q
2.5V / 2.5V or 1.8V
2.5V / 2.5V or 1.8V
2.5V / 2.5V or 1.8V
1.8V / 1.8V
1.8V / 1.8V
1.8V / 1.8V
2.5V / 2.5V or 1.8V
2.5V / 2.5V or 1.8V
2.5V / 2.5V or 1.8V
1.8V / 1.8V
1.8V / 1.8V
1.8V / 1.8V
ARCHITECTURE
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
PACKAGE
54-BALL
VFBGA
54-BALL
VFBGA
54-BALL
VFBGA
54-BALL
VFBGA
54-BALL
VFBGA
54-BALL
VFBGA
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
54-PIN TSOP
Note: 1. Lead-Free packaging partnumbers: Replace the FN with BN for VFBGA and replace the TG code with P for TSOP.
GENERAL DESCRIPTION
The 512Mb Mobile SDRAM is a high-speed CMOS,
dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 134,217,728-bit banks is orga-
nized as 8,192 rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 512Mb Mobile SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while access-
ing one of the other three banks will hide the precharge
cycles and provide seamless, high-speed, random-ac-
cess operation.
The 512Mb Mobile SDRAM is designed to operate in
2.5V or 1.8V memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
09005aef80d053fa
MobileRamY27L_A.p65 – Pub. 07/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
ADVANCE
512Mb: x16
MOBILE SDRAM
TABLE OF CONTENTS
Functional
Block Diagram – 32 Meg x 16 ..............
54-Ball VFBGA Pin Description ................................
54-Pin TSOP Pin Description .....................................
Functional Description
..........................................
Initialization ...........................................................
Register Definition .................................................
Mode Register ...................................................
Burst Length ................................................
Burst Type ....................................................
CAS Latency ................................................
Operating Mode .........................................
Write Burst Mode .......................................
Extended Mode Register ............................
Temperature Compensated Self Refresh .
Partial Array Self Refresh ...........................
Deep Power Down .....................................
Driver Strength ...........................................
Commands
..................................................................
Truth Table 1 (Commands and DQM Operation)
..............
Command Inhibit .................................................
No Operation (NOP) ............................................
Load mode register ................................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge .................................................................
Auto Precharge .......................................................
Auto Refresh ...........................................................
Self Refresh ..............................................................
Operation
....................................................................
Bank/Row Activation ...........................................
Reads .......................................................................
Writes .......................................................................
Precharge .................................................................
Power-Down ..........................................................
Deep Power-Down ................................................
Clock Suspend ........................................................
Burst Read/Single Write ........................................
5
6
7
8
8
8
8
8
9
10
10
10
11
11
12
12
12
13
13
14
14
14
14
14
14
14
14
14
15
16
16
17
23
25
25
26
26
27
Concurrent Auto Precharge .................................
Truth Table 2 (CKE)
.....................................................
Truth Table 3 (Current State, Same Bank)
......................
Truth Table 4 (Current State, Different Bank)
.................
Absolute Maximum Ratings ......................................
DC Electrical Characteristics
and Operating Conditions .................................
Capacitance ..................................................................
28
30
31
32
35
35
36
AC Electrical Characteristics
(Timing Table) ..... 37
I
DD
Specifications and Conditions ........................... 39
Timing Waveforms
Initialize and Load mode register .......................
Power-Down Mode ...............................................
Clock Suspend Mode ............................................
Auto Refresh Mode ...............................................
Self Refresh Mode ..................................................
Reads
Read – Without Auto Precharge ...................
Read – With Auto Precharge ..........................
Single Read – Without Auto Precharge .......
Single Read – With Auto Precharge ..............
Alternating Bank Read Accesses .....................
Read – Full-Page Burst .....................................
Read – DQM Operation .................................
Writes
Write – Without Auto Precharge ..................
Write – With Auto Precharge ........................
Single Write - Without Auto Precharge .......
Single Write - Without Auto Precharge .......
Alternating Bank Write Accesses ...................
Write – Full-Page Burst ....................................
Write – DQM Operation ................................
54-pin TSOP ...........................................................
54-pin VFBGA ........................................................
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
09005aef80d053fa
MobileRamY27L_A.p65 – Pub. 07/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
ADVANCE
512Mb: x16
MOBILE SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 16 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 13
COUNTER
12
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 16)
2
2
DQML,
DQMH
SENSE AMPLIFIERS
16
8192
DATA
OUTPUT
REGISTER
2
A0-A12,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
15
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
16
1024
(x16)
16
DQ0-
DQ15
2
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
10
09005aef80d053fa
MobileRamY27L_A.p65 – Pub. 07/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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