1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
18Mb QDR SRAM
2-WORD BURST
Features
• Separate independent read and write data ports
with concurrent transactions
• 100 percent bus utilization DDR READ and WRITE
operation
• High frequency operation with future migration to
higher clock frequencies
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst counter for low DDR transaction size
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• 2.5V core and 1.5 to 1.8V (±0.1V) HSTL I/O
• Clock-stop capability
• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA
package
• User-programmable impedance output
• JTAG boundary scan
™
MT54V1MH18A
MT54V512H36A
Figure 1: 165-Ball FBGA
Table 1:
Valid Part Numbers
DESCRIPTION
1 Meg x 18, QDRb2 FBGA
512K x 36, QDRb2 FBGA
PART NUMBER
MT54V1MH18AF-xx
MT54V512H36AF-xx
General Description
Options
• Clock Cycle Timing
6ns (167 MHz)
7.5ns (133 MHz)
10ns (100 MHz)
• Configurations
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C
£
T
A
£
+70°C)
NOTE:
Marking
1
-6
-7.5
-10
MT54V1MH18A
MT54V512H36A
F
None
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
The Micron
®
QDR™ (Quad Data Rate™) synchro-
nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process.
The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on rising edges of the K and K# input clocks, respec-
tively. Each address location is associated with two
words that burst sequentially into or out of the device.
Since data can be transferred into and out of the device
on every rising edge of both clocks (K and K# and C
and C#), memory bandwidth is maximized and system
design is simplified by eliminating bus turnarounds.
18Mb: 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
1
©2003 Micron Technology, Inc.
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
Depth expansion is accomplished with port selects
for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation.
All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest and ending with the highest
address. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
The SRAM operates from a 2.5V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
READ cycles are pipelined. The request is initiated
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of the next K, using C and C#
as the output timing references; or K and K#, if C and
C# are tied HIGH. If C and C# are tied HIGH, they may
not be toggled during device operation. Output tri-
stating is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex output enable
(OE) timing generation. Back-to-back READ cycles are
initiated every K rising edge.
WRITE cycles are initiated by W# LOW at K rising
edge. The addresses for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K that
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and pro-
vide fully coherent data for all combinations of reads
and writes. A read can immediately follow a write, even
if they are to the same address. Although the write data
has not been written to the memory array, the SRAM
will deliver the data from the write register instead of
using the older data from the memory array. The latest
data is always utilized for all bus transactions. WRITE
cycles can be initiated on every K rising edge.
BYTE WRITE Operations
BYTE WRITE operations are supported. The active
LOW byte write controls are registered coincident with
their corresponding data. This feature can eliminate
the need for some READ-MODIFY-WRITE cycles, col-
lapsing it to a single BYTE WRITE operation in some
instances.
READ/WRITE Operations
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
transactions can remain in operation on both buses
provided that the address rate can be maintained by
the system (2x the clock frequency).
18Mb: 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
Programmable Impedance Output
Buffer
The QDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175
W
to 350
W
. Alternately, the ZQ ball
can be connected directly to V
DD
Q, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. Impedance updates are transparent to the sys-
tem; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
It is strontly recommended that the clocks operate for
a number of cycles prior to initiating commands to the
SRAM. This delay permits transmission line charging
effects to be overcome and allows the clock timing to
be nearer to its steady-state value.
Single Clock Mode
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
The output echo clocks are precise references to
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
Depth Expansion
Port select inputs are provided for the read and
write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselecting.
Clock Considerations
This device does not utilize internal phase-locked
loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
18Mb: 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
Figure 2: Functional Block Diagram
1 Meg x 18; 512K x 36
n
ADDRESS
R#
W#
K
K#
n
ADDRESS
REGISTRY
& LOGIC
W#
BW0#
BW1#
D (Data In)
R#
K
K#
a
DATA
REGISTRY
& LOGIC
a
WR
R E
I G
T
E 2
WD
R R
I I
T V
E E
R
2 xa
MEMORY
ARRAY
n
S
E A
NM
S P
E S
a
MUX
RO
E U
G T
P
AU
T
C
C, C#
or
K, K#
a
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
Q
(Data Out)
2
K
CQ, CQ#
(Echo Clock Out)
NOTE:
1. Figure 2 illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed
information.
2. For 1 Meg x 18, n = 18, a = 18.
3. For 512K x 36, n = 18, a = 36.
18Mb: 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
Figure 3: Application Example
SRAM 1
Vt
R
D
SA
R = 250Ω
ZQ
Q
CQ
CQ#
C C# K K#
SRAM 2
R = 250Ω
ZQ
Q
CQ
CQ#
C C# K K#
B
R W W
# # #
D
SA
B
R W W
# # #
BUS
MASTER
SRAM 1 Input CQ
(CPU
SRAM 1 Input CQ#
SRAM 2 Input CQ
or
SRAM 2 Input CQ#
ASIC)
DATA IN
DATA OUT
Address
Read#
Write#
BW#
R
Vt
Vt
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
NOTE:
1. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
2. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
3. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
18Mb: 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
