Integrated
Circuit
Systems, Inc.
ICS9248-195
Frequency Generator & Integrated Buffers for PENTIUM
II III
TM
& K6
Recommended Application:
Key Specifications:
• CPU Output Jitter @ 2.5V: <300ps
440BX, MX, VIA PM/PL/PLE 133 style chip set, with
• CPU Output Jitter @ 3.3V: <250ps
Coppermine or Tualatin processor, for note book
• PCI Output Jitter @ 3.3V: <250ps
applications.
• CPU Output Skew @ 2.5V: <175ps
Output Features:
• CPU Output Skew @ 3.3V: <175ps
•
4 - CPUs @ 2.5V/3.3V
• PCI Output Skew @ 3.3V: <500ps
including 1 free running CPUCLK_F
• PCI Early to PCI Skew @ 3.3V: typ = 3ns
•
9 - SDRAM @ 3.3V
• SDRAM Output Skew @ 3.3V: <500ps
•
7 - PCI @ 3.3V, including 1 free running PCICLK_F
• 1 - PCI Early @ 3.3V
Pin Configuration
•
1 - 48MHz, @ 3.3V fixed.
48
REF1/FS2*
VDDREF
1
47
VDDLCPU
*SPREAD/REF0
2
•
1 - 24/48MHz @ 3.3V
46
CPUCLK_F
GNDREF
3
•
2 - REF @3.3V, 14.318MHz.
45
CPUCLK0
4
X1
44
GNDLCPU
5
X2
Features:
43
CPUCLK1
6
VDDPCI
42
CPUCLK2
7
*CPU2.5_3.3#/PCICLK_F
• Up to 137MHz frequency support
41
CLK_STOP#
8
*FS3/PCICLK0
40
GNDSDR
9
GNDPCI
• 97MHz to support high-end AMD processor.
39
SDRAM_F
10
*SEL24_48#/PCICLK1
• Support power management: CLK, PCI, stop and
38
SDRAM0
11
*SELPCIE_6#/PCICLK2
37
SDRAM1
12
PCICLK3
Power down Mode from I
2
C programming.
36
VDDSDR
13
PCICLK4
35
• Spread spectrum for EMI control
SDRAM2
14
VDDPCI
34
SDRAM3
15
BUFFER IN
• Uses external 14.318MHz crystal
33
GNDSDR
16
GNDPCI
32
SDRAM4
17
PCICLK5
• FS pins for frequency select
31
SDRAM5
18
PCICLK6/PCICLK_E
ICS9248-195
VDDCOR
PCI_STOP#
*Vtt_PWRGD/PD#
GND48
SDATA
SCLK
19
20
21
22
23
24
30
29
28
27
26
25
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of 120K to VDD
Functionality
Bit2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
66.67
100.00
66.67
133.33
66.67
100.00
100.00
133.33
66.67
100.00
90.00
133.33
70.00
105.00
133.33
140.00
PCICLK
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
30.00
33.33
35.00
35.00
33.33
35.00
0375E—12/15/08
ICS9248-195
Pin Descriptions
PIN
NUMBER
1
2
20
3, 9, 16,
33, 40, 44
4
5
6,14
7
8
10
11
17, 13, 12
15
18
19
PIN NAME
VDDREF
S P R E A D
1,2
REF0
PCI_STOP#
GND
X1
X2
VDDPCI
C P U 2 . 5 _ 3 . 3 #
1,2
PCICLK_F
F S3
1 , 2
PCICLK0
SEL24_48#
PCICLK1
PCICLK2
PCICLK (5:3)
BUFFER IN
PCICLK6/PCICLK_-
E
VDDCOR
Vtt_PWRGND
21
PD#
1
22
28, 29, 31, 32,
34, 35, 37, 38
30, 36
23
24
25
26
27
39
41
42, 43, 45
46
47
48
GND48
SDRAM (7:0)
VDDSDR
SDATA
SCLK
24_48MHz
FS1
1, 2
48MHz
FS0
1, 2
VDD48
SDRAM_F
CLK_STOP#
CPUCLK (2:0)
CPUCLK_F
VDDLCPU
REF1
FS2
1, 2
IN
PWR
OUT
PWR
IN
IN
OUT
IN
OUT
IN
PWR
OUT
IN
OUT
OUT
PWR
OUT
IN
1,2
TYPE
PWR
IN
OUT
IN
PWR
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
PWR
IN
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Active High Spread Spectr um enable input. Power-up default is "High", spreading is "on"
14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads
Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0)
Ground
Cr ystal input, has inter nal load cap (36pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz.
Supply for PCICLK_F and PCICLK nominal 3.3V
Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power management.
Frequency select pin. Latched Input.
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Selects either 24 or 48MHz when Low =48 MHz
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
PCI Early or normal PCI select latch input. (for pin 18 power-up default is "High" early PCICLK.)
PCICLK clock output.
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Input to Fanout Buffers for SDRAM outputs.
PCI clock output or ear ly PCI clock output selectable by SELPCIE_6#
Power pin for the PLL core. 3.3V
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD
g o e s h i g h t h e f r e q u e n c y s e l e c t w i l l b e l a t c h e d a t p ow e r o n t h e r e a f t e r t h e p i n i s a n
asynchronous active low power down pin.
Asynchronous active low input pin used to power down the device into a low power state. The
inter nal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the
p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 4 m s.
Ground pin for the 24 & 48MHz output buffers & fixed PLL core.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset).
Supply for SDRAM and CPU PLL Core, nominal 3.3V.
Data input for I
2
C serial input, 5V tolerant input
Clock input of I
2
C input, 5V tolerant input
24MHz or 48MHz output clock selectable by pin 10
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK, & SDRAM at logic "0" level when driven low.
CPU clock outputs, powered by VDDLCPU
Free running CPU clock. Not affected by the CPU_STOP#
Supply for CPU clocks 2.5V
14.318 MHz reference clock.
Frequency select pin. Latched Input
SELPCIE_6#
1,2
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0375E—12/15/08
2
ICS9248-195
General Description
The
ICS9248-195
is the single chip clock solution for Notebook designs using the 440BX, MX, VIA PM/PL/PLE 133
style chip set, with Coppermine or Tualatin processor, for Note book applications. It provides all necessary clock signals
for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9248-
195
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Description
0 = Center Spread Spectrum Modulation
1 = Down Spread Spectrum Modulation
FS3 FS2 FS1 FS0
CPUCLK
Bit2 Bit6 Bit5 Bit4
PCICLK
Center
Spread %
Down
Spread%
PWD
1
Bit 2,
6:4
Bit 3
Bit 1
Bit 0
0
0
0
0
66.67
33.33
±0.35%
-0.70%
0
0
0
1
100.00
33.33
±0.35%
-0.70%
0
0
1
0
66.67
33.33
±0.60%
-1.20%
0
0
1
1
133.33
33.33
±0.35%
-0.70%
0
1
0
0
66.67
33.33
±0.23%
-0.45%
0
1
0
1
100.00
33.33
±0.23%
-0.45%
0
1
1
0
100.00
33.33
±0.60%
-1.20%
0
1
1
1
133.33
33.33
±0.23%
-0.45%
1
0
0
0
66.67
33.33
±0.45%
-0.90%
1
0
0
1
100.00
33.33
±0.45%
-0.90%
1
0
1
0
90.00
30.00
±0.35%
-0.70%
1
0
1
1
133.33
33.33
±0.45%
-0.90%
1
1
0
0
70.00
35.00
±0.35%
-0.70%
1
1
0
1
105.00
35.00
±0.35%
-0.70%
1
1
1
0
133.33
33.33
±0.60%
-1.20%
1
1
1
1
140.00
35.00
±0.35%
-0.70%
0 - Frequency is selected by hardware select pins. Latched inputs.
1 - Frequency is controlled by I
2
C programming.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
Note1
0011
0
1
0
Notes:
1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011.
2, PWD = Power-Up Default
0375E—12/15/08
3
ICS9248-195
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
46
-
-
39
42
43
45
PWD
1
1
0
0
1
1
1
1
Description
(Reserved)
CPUCLK_F (En/Dis)
(Reserved)
(Reserved)
SDRAM_F (En/Dis)
CPUCLK2 (En/Dis)
CPUCLK1 (En/Dis)
CPUCLK0 (En/Dis)
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
7
18
17
13
12
11
10
8
PW D
1
1
1
1
1
1
1
1
Description
PCICLK_F (En/Dis)
PCICLK6 (En/Dis)
PCICLK5 (En/Dis)
PCICLK4 (En/Dis)
PCICLK3 (En/Dis)
PCICLK2 (En/Dis)
PCICLK1 (En/Dis)
PCICLK0 (En/Dis)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
28
29
31
32
PW D
1
0
0
0
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM7 (En/Dis)
SDRAM6 (En/Dis)
SDRAM5 (En/Dis)
SDRAM4 (En/Dis)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to
be floating (pulled up via internal resistor) at power-up.
0375E—12/15/08
4
ICS9248-195
Byte 4: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
PWD
1
0
0
0
0
0
0
1
Description
(Reserved)
(Reserved)
(SEL24_48)#
Latched FS0#
Latched FS1#
Latched FS2#
Latched FS3#
(Reserved)
Byte 5: Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
35
37
38
26
25
48
2
PWD
1
1
1
1
1
1
1
1
Description
SDRAM3 (En/Dis)
SDRAM2 (En/Dis)
SDRAM1 (En/Dis)
SDRAM0 (En/Dis)
48MHz (En/Dis)
24MHz (En/Dis)
REF1 (En/Dis)
REF0 (En/Dis)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to be floating
(pulled up via internal resistor) at power-up.
0375E—12/15/08
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
