Datasheet> 器件分类 > 存储> 存储> MT49H16M36BM-25:A

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MT49H16M36BM-25:A: 产品描述DDR DRAM, 16MX36, 20ns, CMOS, PBGA144, LEAD FREE, UBGA-144; 产品类别存储存储; 文件大小1MB，共82页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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MT49H16M36BM-25:A概述

DDR DRAM, 16MX36, 20ns, CMOS, PBGA144, LEAD FREE, UBGA-144

MT49H16M36BM-25:A规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Micron Technology
零件包装代码	BGA
包装说明	LEAD FREE, UBGA-144
针数	144
Reach Compliance Code	unknown
ECCN代码	EAR99
访问模式	MULTI BANK PAGE BURST
最长访问时间	20 ns
其他特性	AUTO REFRESH
最大时钟频率 (fCLK)	400 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B144
JESD-609代码	e1
长度	18.5 mm
内存密度	603979776 bit
内存集成电路类型	DDR DRAM
内存宽度	36
功能数量	1
端口数量	1
端子数量	144
字数	16777216 words
字数代码	16000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	16MX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TBGA
封装等效代码	BGA144,12X18,40/32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE
峰值回流温度（摄氏度）	260
电源	1.5/1.8,1.8,2.5 V
认证状态	Not Qualified
座面最大高度	1.2 mm
连续突发长度	2,4,8
最大待机电流	0.048 A
最大压摆率	1.1 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	11 mm

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576Mb: x9 x18 x36 CIO RLDRAM 2

Features

CIO RLDRAM 2

MT49H64M9 – 64 Meg x 9 x 8 Banks

MT49H32M18 – 32 Meg x 18 x 8 Banks

MT49H16M36 – 16 Meg x 36 x 8 Banks

Features

• 533 MHz DDR operation (1.067 Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock

frequency)

• Organization

– 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O

– 8 banks

• Reduced cycle time (15ns at 533 MHz)

• Nonmultiplexed addresses (address multiplexing

option available)

• SRAM-type interface

• Programmable READ latency (RL), row cycle time,

and burst sequence length

• Balanced READ and WRITE latencies in order to op-

timize data bus utilization

• Data mask for WRITE commands

• Differential input clocks (CK, CK#)

• Differential input data clocks (DKx, DKx#)

• On-die DLL generates CK edge-aligned data and

output data clock signals

• Data valid signal (QVLD)

• 32ms refresh (16K refresh for each bank; 128K re-

fresh command must be issued in total each 32ms)

• HSTL I/O (1.5V or 1.8V nominal)

•

–Ω

matched impedance outputs

• 2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

DDQ

I/O

• On-die termination (ODT) R

Options

• Clock cycle timing

– 1.875ns @

RC = 15ns

– 2.5ns @

RC = 15ns

– 2.5ns @

RC = 20ns

– 3.3ns @

RC = 20ns

• Configuration

– 64 Meg x 9

– 32 Meg x 18

– 16 Meg x 36

• Operating temperature

– Commercial (0° to +95°C)

– Industrial (T

= –40°C to +95°C;

= –40°C to +85°C)

• Package

– 144-ball μBGA

– 144-ball μBGA (Pb-free)

– 144-ball FBGA

– 144-ball FBGA (Pb-free)

• Revision

Note:

Marking

-18

-25E

-25

-33

64M9

32M18

16M36

None

:A/:B

1. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on

www.micron.com

for availa-

ble offerings.

PDF: 09005aef80fe62fb

576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

576Mb: x9 x18 x36 CIO RLDRAM 2

Features

Contents

General Description ......................................................................................................................................... 7

Functional Block Diagrams ............................................................................................................................... 8

Ball Assignments and Descriptions ................................................................................................................. 11

Package Dimensions ....................................................................................................................................... 16

Electrical Specifications – I

.......................................................................................................................... 18

Absolute Maximum Ratings ............................................................................................................................ 22

AC and DC Operating Conditions .................................................................................................................... 23

Input Slew Rate Derating ................................................................................................................................ 26

Notes ............................................................................................................................................................. 31

Temperature and Thermal Impedance ............................................................................................................ 32

Commands .................................................................................................................................................... 34

MODE REGISTER SET (MRS) ...................................................................................................................... 35

Configuration Tables .............................................................................................................................. 37

Burst Length (BL) ................................................................................................................................... 37

Address Multiplexing .............................................................................................................................. 39

DLL RESET ............................................................................................................................................. 39

Drive Impedance Matching .................................................................................................................... 39

On-Die Termination (ODT) ..................................................................................................................... 40

WRITE ....................................................................................................................................................... 41

READ ......................................................................................................................................................... 42

AUTO REFRESH (AREF) .............................................................................................................................. 43

INITIALIZATION ............................................................................................................................................ 43

WRITE ........................................................................................................................................................... 47

READ ............................................................................................................................................................. 52

AUTO REFRESH ............................................................................................................................................. 60

On-Die Termination ....................................................................................................................................... 61

Multiplexed Address Mode .............................................................................................................................. 64

Address Mapping in Multiplexed Address Mode ........................................................................................... 67

Configuration Tables in Multiplexed Address Mode ...................................................................................... 67

REFRESH Command in Multiplexed Address Mode ..................................................................................... 68

IEEE 1149.1 Serial Boundary Scan (JTAG) ........................................................................................................ 72

Disabling the JTAG Feature ......................................................................................................................... 72

Test Access Port (TAP) ..................................................................................................................................... 72

Test Clock (TCK) ......................................................................................................................................... 72

Test Mode Select (TMS) .............................................................................................................................. 72

Test Data-In (TDI) ...................................................................................................................................... 73

Test Data-Out (TDO) .................................................................................................................................. 73

TAP Controller ................................................................................................................................................ 73

Test-Logic-Reset ......................................................................................................................................... 73

Run-Test/Idle ............................................................................................................................................. 73

Select-DR-Scan .......................................................................................................................................... 73

Capture-DR ................................................................................................................................................ 73

Shift-DR ..................................................................................................................................................... 73

Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 74

Update-DR ................................................................................................................................................. 74

Instruction Register States .......................................................................................................................... 74

Performing a TAP RESET ................................................................................................................................. 75

TAP Registers ................................................................................................................................................. 75

Instruction Register .................................................................................................................................... 75

Bypass Register .......................................................................................................................................... 75

PDF: 09005aef80fe62fb

576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

576Mb: x9 x18 x36 CIO RLDRAM 2

Features

List of Figures

Figure 1: Part Numbers .................................................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................... 7

Figure 3: 64 Meg x 9 Functional Block Diagram ................................................................................................. 8

Figure 4: 32 Meg x 18 Functional Block Diagram ............................................................................................... 9

Figure 5: 16 Meg x 36 Functional Block Diagram ............................................................................................. 10

Figure 6: 144-Ball μBGA ................................................................................................................................. 16

Figure 7: 144-Ball FBGA ................................................................................................................................. 17

Figure 8: Clock Input ..................................................................................................................................... 25

Figure 9: Nominal

AS/

CS/

DS and

AH/

CH/

DH Slew Rate ........................................................................... 29

Figure 10: Example Temperature Test Point Location ...................................................................................... 33

Figure 11: MODE REGISTER Command ......................................................................................................... 35

Figure 12: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 36

Figure 13: Read Burst Lengths ........................................................................................................................ 38

Figure 14: On-Die Termination-Equivalent Circuit .......................................................................................... 40

Figure 15: WRITE Command ......................................................................................................................... 41

Figure 16: READ Command ........................................................................................................................... 42

Figure 17: AUTO REFRESH Command ........................................................................................................... 43

Figure 18: Power-Up/Initialization Sequence ................................................................................................. 45

Figure 19: Power-Up/Initialization Flow Chart ................................................................................................ 46

Figure 20: WRITE Burst ................................................................................................................................. 47

Figure 21: Consecutive WRITE-to-WRITE ....................................................................................................... 48

Figure 22: WRITE-to-READ ............................................................................................................................ 49

Figure 23: WRITE-to-READ (Separated by Two NOPs) ..................................................................................... 50

Figure 24: WRITE – DM Operation ................................................................................................................. 51

Figure 25: Basic READ Burst Timing ............................................................................................................... 52

Figure 26: Consecutive READ Bursts (BL = 2) .................................................................................................. 53

Figure 27: Consecutive READ Bursts (BL = 4) .................................................................................................. 53

Figure 28: READ-to-WRITE ............................................................................................................................ 54

Figure 29: Read Data Valid Window for x9 Device ........................................................................................... 55

Figure 30: Read Data Valid Window for x18 Device .......................................................................................... 56

Figure 31: Read Data Valid Window for x36 Device .......................................................................................... 58

Figure 32: AUTO REFRESH Cycle ................................................................................................................... 60

Figure 33: READ Burst with ODT .................................................................................................................... 61

Figure 34: READ-NOP-READ with ODT .......................................................................................................... 62

Figure 35: READ-to-WRITE with ODT ............................................................................................................ 63

Figure 36: Command Description in Multiplexed Address Mode ..................................................................... 64

Figure 37: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 65

Figure 38: Mode Register Definition in Multiplexed Address Mode .................................................................. 66

Figure 39: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 68

Figure 40: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 68

Figure 41: WRITE-to-READ with Multiplexed Addressing ................................................................................ 69

Figure 42: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 70

Figure 43: READ-to-WRITE with Multiplexed Addressing ................................................................................ 70

Figure 44: TAP Controller State Diagram ......................................................................................................... 74

Figure 45: TAP Controller Block Diagram ........................................................................................................ 75

Figure 46: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 78

Figure 47: TAP Timing ................................................................................................................................... 79

PDF: 09005aef80fe62fb

576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT49H16M36BM-25:A相似产品对比

	MT49H16M36BM-25:A	MT49H64M9BM-25:B	MT49H32M18BM-25E:B	MT49H16M36FM-25E:B	MT49H16M36FM-18:B	MT49H32M18FM-25:B	MT49H16M36BM-25:B
描述	DDR DRAM, 16MX36, 20ns, CMOS, PBGA144, LEAD FREE, UBGA-144	DDR DRAM, 64MX9, 20ns, CMOS, PBGA144, LEAD FREE, UBGA-144	DDR DRAM, 32MX18, 15ns, CMOS, PBGA144, LEAD FREE, UBGA-144	DDR DRAM, 16MX36, 15ns, CMOS, PBGA144, UBGA-144	DDR DRAM, 16MX36, 15ns, CMOS, PBGA144, UBGA-144	DDR DRAM, 32MX18, 20ns, CMOS, PBGA144, UBGA-144	DDR DRAM, 16MX36, 20ns, CMOS, PBGA144, LEAD FREE, UBGA-144
是否Rohs认证	符合	符合	符合	不符合	不符合	不符合	符合
厂商名称	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	LEAD FREE, UBGA-144	LEAD FREE, UBGA-144	LEAD FREE, UBGA-144	UBGA-144	UBGA-144	UBGA-144	LEAD FREE, UBGA-144
针数	144	144	144	144	144	144	144
Reach Compliance Code	unknown	compliant	compliant	not_compliant	not_compliant	not_compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
最长访问时间	20 ns	20 ns	15 ns	15 ns	15 ns	20 ns	20 ns
其他特性	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH
最大时钟频率 (fCLK)	400 MHz	400 MHz	400 MHz	400 MHz	533 MHz	400 MHz	400 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144	R-PBGA-B144
JESD-609代码	e1	e1	e1	e0	e0	e0	e1
长度	18.5 mm	18.5 mm	18.5 mm	18.5 mm	18.5 mm	18.5 mm	18.5 mm
内存密度	603979776 bit	603979776 bit	603979776 bit	603979776 bit	603979776 bit	603979776 bit	603979776 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	36	9	18	36	36	18	36
功能数量	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1
端子数量	144	144	144	144	144	144	144
字数	16777216 words	67108864 words	33554432 words	16777216 words	16777216 words	33554432 words	16777216 words
字数代码	16000000	64000000	32000000	16000000	16000000	32000000	16000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	16MX36	64MX9	32MX18	16MX36	16MX36	32MX18	16MX36
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TBGA	TBGA	TBGA	TBGA	TBGA	TBGA	TBGA
封装等效代码	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32	BGA144,12X18,40/32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
电源	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V	1.5/1.8,1.8,2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
连续突发长度	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
最大待机电流	0.048 A	0.055 A	0.055 A	0.055 A	0.055 A	0.055 A	0.055 A
最大压摆率	1.1 mA	0.655 mA	0.655 mA	0.7 mA	0.885 mA	0.655 mA	0.7 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm

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器件捷径: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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