MR16R0824(6/8/C/G)AN1
MR18R0824(6/8/C/G)AN1
Change History
Version 1.0 (August 1999)
- Preliminary
* First copy.
* Based on the Rambus RIMM Datasheet Rev.1.0.
Version 1.01 (October 1999)
Page No.
Change Description
- Delete the part numbers of low power.
- Add the plate temperature value,
T
PLATE
to 92
°C.
- Correct the Component height.
- Correct the tolerance from
±0.13mm
to
±0.127mm.
- Correct the heat spreader thickness on double sided modules to 7.07±0.30mm.
- Change the marked text of Standard RIMM Module Marking Information as follows
* from "16d,12d,8d,6d,4d" to "/16,/12,/8,/6,/4" @ Number of RDRAMs
* to "Gerber : 10 = 1.0ver / SPD : 0 = 1.0ver" @ Gerber & SPD version Field.
* from 53.3 to 53 @ tRAC Field.
1
6
10
11
12
Version 1.02 (January 2000)
* Change the part number of RIMM Module based upon to New Code System since ’00.Jan.1st
Page No.
Change Description
- Relax CMOS impedance for CMD,SCK from 28
Ω
±10%
to 28
Ω
±15%.
- Change the heat spreader thickness including PCB to max. 7.80mm for double sided RIMM and max.
4.70mm for single sided RIMM.
8
11
Version 1.1 (October 2000)
* Update based on the latest Rambus RIMM Datasheet
Page No.
Change Description
6
8
- Correct V
CMOS
to V
DD
& Add V
SPD
condition
- Change the symbol of module impedance
: From (Z) Module Impendance for RSL & CMOS To
(Z
L
)
for RSL and
(Z
UL-CMOS
)
for SCK, CMOS
- Relax the RIMM CMOS delta tPD spec. from
±100ps
to
±250ps
- Add delta tPD spec for SCK-CMD of
±200ps
- Relax tPD as follows
16d
OLD
(-800 & -711MHz/-600MHz)
9
8d
1.50 / 1.60ns
1.56ns
4d
1.25ns
1.28ns
2.06 / 2.10ns
2.11ns
NEW
(-800,-711&-600MHz)
Page -1
Version 1.1 Oct. 2000
MR16R0824(6/8/C/G)AN1
MR18R0824(6/8/C/G)AN1
(8Mx16)*4(6/8/12/16)pcs RIMM
TM
Module based on 128Mb A-die, 32s banks,16K/32ms Ref, 2.5V
(8Mx18)*4(6/8/12/16)pcs RIMM
TM
Module based on 144Mb A-die, 32s banks,16K/32ms Ref, 2.5V
Overview
The Rambus
®
RIMM™ module is a general purpose high-
performance memory module suitable for use in a broad
range of applications including computer memory, personal
computers, workstations, and other applications where high
bandwidth and low latency are required.
The Rambus RIMM module consists of 128Mb/144Mb
Direct Rambus DRAM devices. These are extremely high-
speed CMOS DRAMs organized as 8M words by 16 or 18
bits. The use of Rambus Signaling Level (RSL) technology
permits 600 MHz, 711 MHz or 800 MHz transfer rates while
using conventional system and board design technologies.
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per 16 bytes).
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM's 32-bank architecture supports
up to four simultaneous transactions per device.
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available for RIMM modules.
Table 1: Part Number by Freq. & Latency
Speed
Organiza-
tion
I/O Freq.
(MHz)
800
711
600
800
711
600
800
711
600
800
711
600
800
711
600
t
RAC
(Row
Access
Time) ns
45
45
53.3
45
45
53.3
45
45
53.3
45
45
53.3
45
45
53.3
Part Number
Bin
32M x 16/18 -CK8
-CK7
-CG6
48M x 16/18 -CK8
-CK7
-CG6
64M x 16/18 -CK8
-CK7
-CG6
96M x 16/18 -CK8
MR16/18R0824AN1-CK8
MR16/18R0824AN1-CK7
MR16/18R0824AN1-CG6
MR16/18R0826AN1-CK8
MR16/18R0826AN1-CK7
MR16/18R0826AN1-CG6
MR16/18R0828AN1-CK8
MR16/18R0828AN1-CK7
MR16/18R0828AN1-CG6
MR16/18R082CAN1-CK8
MR16/18R082CAN1-CK7
MR16/18R082CAN1-CG6
MR16/18R082GAN1-CK8
MR16/18R082GAN1-CK7
MR16/18R082GAN1-CG6
Features
♦
High speed 800, 711 and 600MHz RDRAM storage
♦
184 edge connector pads with 1mm pad spacing
♦
Module PCB size : 133.35mm x 31.75mm x1.27mm
-CK7
-CG6
128M x 16/18 -CK8
-CK7
-CG6
(5.25” x 1.25” x 0.05”)
♦
Each RDRAM has 32 banks, for a total of 512, 384, 256,
192, or 128 banks on each 256/288MB, 192/216MB,
128/144MB, 96/108MB, or 64/72MB module respectively
♦
Gold plated edge connector pad contacts
♦
Serial Presence Detect(SPD) support
♦
Operates from a 2.5 volt supply (±5%)
♦
Powerdown self refresh modes
♦
Separate Row and Column buses for higher efficiency
♦ µ-
BGA package (62 Balls)
Form Factor
The Rambus RIMM modules are offered in 184-pad 1mm
edge connector pad pitch suitable for 184 contact RIMM
connectors. Figure 1 below, shows a sixteen device Rambus
RIMM module.
Note: On double sided modules, RDRAMs are also installed on bottom side of PCB.
Figure 1: Rambus RIMM Module shown with heat spreader removed
Page 2
Version 1.1 Oct. 2000
MR16R0824(6/8/C/G)AN1
MR18R0824(6/8/C/G)AN1
Table 3: Module Connector Pad Description
Signal
Gnd
Pins
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
B10
B12
I
RSL
I/O
Type
Description
Ground reference for RDRAM core and interface. 72 PCB
connector pads.
LCFM
LCFMN
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command used to read from and write to the control
registers. Also used for power management.
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. LDQA8 is non-func-
tional on modules with x16 RDRAM devices
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. LDQB8 is non-func-
tional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information
for row accesses.
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
These pads are not connected. These 24 connector pads are
reserved for future use.
I
I
RSL
V
CMOS
RSL
RSL
LCMD
LCOL4..
LCOL0
LCTM
LCTMN
B34
A20, B20, A22, B22, A24
I
I
A14
A12
I
RSL
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
I/O
RSL
LDQB8..
LDQB0
LROW2..
LROW0
LSCK
NC
B32, A32, B30, A30, B28, A28, B26,
A26, B24
B16, A18, B18
I/O
RSL
I
I
RSL
V
CMOS
A34
A16, B14, A38, B38, A40, B40, A43,
B43, A44, B44, A45, B45, A46, B46,
A47, B47, A48, B48, A49, B49, A50,
B50, A77, B79
B83
RCFM
I
I
RSL
RSL
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command Input. Pin used to read from and write to the
control registers. Also used for power management.
RCFMN
RCMD
B81
B59
I
V
CMOS
Page 4
Version 1.1 Oct. 2000
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