64MB, 128MB, 256MB (x72, ECC, SR)
168-PIN SDRAM RDIMM
SYNCHRONOUS
DRAM MODULE
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
168-pin, dual in-line memory module (DIMM)
PC100- and PC133-compliant
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
Utilizes 125 MHz and 133 MHz SDRAM components
Supports ECC error detection and correction
64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of PLL clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes Concurrent Auto
Precharge; Auto Refresh Mode
Self Refresh Mode: 64ms, 4,096-cycle refresh (64MB,
128MB); 8,192 cycle refresh (256MB)
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Gold edge contacts
MT9LSDT872 – 64MB
MT9LSDT1672 – 128MB
MT9LSDT3272 – 256MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.50in. (38.10mm)
Low-Profile 1.125 in. (28.58 mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/CAS Latency
2
133 MHz (7.5ns) / CL = 2
133 MHz (7.5ns) / CL = 3
100 MHz (8ns) / CL = 2
• PCB
Standard 1.50in. (38.10mm)
Low-Profile 1.125in. (28.58mm)
NOTE:
Marking
G
Y
1
-13E
-133
-10E
See page 2 note
See page 2 note
Table 1:
Timing Parameters
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
6ns2
–
5.4ns
–
SETUP HOLD
TIME TIME
1.5ns
1.5ns
2ns
0.8ns
0.8ns
1ns
1. Conact Micron for product availability.
2. Registered mode will add one clock cycle to CL.
Table 2:
Address Table
64MB
4K
4 (BA0, BA1)
64Mb (8 Meg x 8)
4K (A0–A11)
512 (A0–A8)
1 (S0#, S2#)
128MB
4K
4 (BA0, BA1)
128Mb (16 Meg x 8)
4K (A0–A11)
1K (A0–A9)
1 (S0#, S2#)
256MB
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
1 (S0#, S2#)
MODULE DENSITY
Refresh Count
Device Banks
Device Configuration
Device Row Addressing
Device Column Addressing
Module Ranks
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C8_16_32x72G.fm - Rev. B 2/05 EN
1
©2005 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64MB, 128MB, 256MB (x72, ECC, SR)
168-PIN SDRAM RDIMM
Table 3:
Part Numbers
MODULE DENSITY
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
CONFIGURATION
8 Meg x 72
8 Meg x 72
8 Meg x 72
8 Meg x 72
8 Meg x 72
8 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
SYSTEM BUS SPEED
133MHz
133MHz
133MHz
133MHz
100MHz
100MHz
133MHz
133MHz
133MHz
133MHz
100MHz
100MHz
133MHz
133MHz
133MHz
133MHz
100MHz
100MHz
PARTNUMBER
MT9LSDT872G-13E__
MT9LSDT872Y-13E__
MT9LSDT872G-133__
MT9LSDT872Y-133__
MT9LSDT872G-10E__
MT9LSDT872Y-10E__
MT9LSDT1672G-133__
MT9LSDT1672Y-133__
MT9LSDT1672G-13E__
MT9LSDT1672Y-13E__
MT9LSDT1672G-10E__
MT9LSDT1672Y-10E__
MT9LSDT3272G-133__
MT9LSDT3272Y-133__
MT9LSDT3272G-13E__
MT9LSDT3272Y-13E__
MT9LSDT3272G-10E__
MT9LSDT3272Y-10E__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9LSDT1672G-133B1.
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C8_16_32x72G.fm - Rev. B 2/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR)
168-PIN SDRAM RDIMM
Table 4:
Pin Assignment Table
168-Pin DIMM (Front)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
DNU
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
SS
DNU
S2#
DQMB2
DQMB3
DNU
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
Table 5:
Pin Assignment Table
168-Pin DIMM (Back)
106
CB5
127
107
V
SS
128
108
NC
129
109
NC
130
131
110
V
DD
111 CAS# 132
112 DQMB4 133
113 DQMB5 134
NC
135
114
115 RAS# 136
116
V
SS
137
117
A1
138
118
A3
139
119
A5
140
120
A7
141
121
A9
142
122
BA0
143
123
A11
144
145
124
V
DD
125
CK1
146
1
147
126
NC/A12
V
SS
CKE0
RFU (S3#)
DQMB6
DQMB7
RFU (A13)
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
1. Pin 126 is NC (64MB and 128MB) or A12 (256MB).
Figure 2: 168-Pin DIMM Pin Locations
Front View
Standard
Front View
Low-Profile
U4
U1
U2
U3
U4
U1
U5
U7
U9
U2
U3
U5
U6
U6
U7
PIN 1
PIN 41
PIN 84
PIN 1
PIN 41
PIN 84
Back View
Back View
U10
U11
U12
U13
U14
U9
U10
U11
U12
U13
U14
PIN 168
PIN125
PIN 85
PIN 168
PIN125
PIN 85
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C8_16_32x72G.fm - Rev. B 2/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR)
168-PIN SDRAM RDIMM
Table 6:
Pin Descriptions
SYMBOL
WE#, CAS#,
RAS#
CK0–CK3
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
Clock: CK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. CK also increments the
internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides PRECHARGE, POWER-
DOWN, and SELF REFRESH operation (all device banks idle), ACTIVE
POWER-DOWN (row ACTIVE in any device bank), or CLOCK
SUSPEND operation (burst access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CK, are disabled during power-
down and self refresh modes, providing low standby power.
Chip Select: S# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when S#
are registered HIGH. S# are considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input data
is masked when DQMB is sampled HIGH during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency)
when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: sampled during the ACTIVE command and READ/
WRITE command, with A10 defining auto precharge) to select one
location out of the memory array in the respective device bank.
A10 is sampled during a PRECHARGE command to determine if
both device banks are to precharged (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Register Enable.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
27, 111, 115
42, 79, 125, 163
128
CKE0
Input
30, 45
S0#, S2#
Input
28-29, 46-47, 112-113, 130-
131
DQMB0–
DQMB7
Input
39, 122
BA0, BA1
Input
Input
33, 34, 35, 36, 37, 38, 117,
A0–A11
118, 119, 120, 121, 123, 126
(64MB, 128MB)
(256MB)
A0–A12
(256MB)
83
165–167
147
2–5, 7–11, 13–17, 19–20, 55–
58, 60, 65–67, 69–72, 74–77,
86–89, 91–95, 97–101, 103–
104, 139–142, 144, 149–151,
153–156, 158–161
21–22, 52–53, 105–106,
136–137
82
SCL
SA0–SA2
REGE
DQ0–DQ63
Input
Input
Input
Input/
Output
CB0–CB7
SDA
6, 18, 26, 40–41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
V
DD
Input/ Check Bits.
Output
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and data out of the presence-
detect portion of the module.
Supply Power Supply: +3.3V ±0.3V.
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C8_16_32x72G.fm - Rev. B 2/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
64MB, 128MB, 256MB (x72, ECC, SR)
168-PIN SDRAM RDIMM
Table 6:
Pin Descriptions
SYMBOL
TYPE
Supply
Ground.
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127,
138, 148, 152, 162
63, 81, 114, 126 (64MB,
128MB), 129, 132
31, 44, 48
V
SS
NC
DNU
–
–
Reserved for Future Use: These pins are not connected on this
module but are assigned pins on other SDRAM versions.
Do Not Use: These pins are not connected on this module but are
assigned pins on the compatible DRAM version.
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C8_16_32x72G.fm - Rev. B 2/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
