256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
SYNCHRONOUS
DRAM MODULE
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PC100- and PC133-compliant
168-pin, dual in-line memory module (DIMM)
Unbuffered, ECC-optimized pinout
256MB (32 Meg x 72) and 512MB (64 Meg x 72)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes Concurrent Auto
Precharge, and Auto Refresh Modes
Self Refresh Mode
64ms, 8,192-cycle refresh
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Gold edge contacts
MT9LSDT3272(L)A(I) – 256MB
MT18LSDT6472(L)A(I) – 512MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 168-Pin DIMM (MO–161)
Standard 1.375in./34.93mm
Low Profile 1.125in./28.58mm
Options
Marking
Table 1:
Timing Parameters
SETUP
TIME
1.5
1.5
2ns
HOLD
TIME
0.8
0.8
1ns
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
9ns
–
5.4ns
7.5ns
• Operating Temperature Range
None
Commercial (0°C to +65°C)
Industrial (-40°C to +85°C)
I
1
• Package
G
168-pin DIMM (Standard)
Y
1
168-pin DIMM (Lead-free)
• Frequency/CAS Latency
-13E
7.5ns (133 MHz)/CL = 2
-133
7.5ns (133 MHz)/CL = 3
-10E
10ns (100 MHz)/CL = 2
• PCB
Standard (1.375in./34.93mm)
See note on page 2
Low-Profile (1.125in./28.58mm) See note on page 2
NOTE:
1. Consult Micron for product availability; Indus-
trial Temperature Option available in -133 speed
only.
Table 2:
Address Table
256MB
512MB
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
2 (S0 #, S2#; S1#, S3#)
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
1 (S0#, S2#)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
Table 3:
Part Numbers
MODULE DENSITY
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
SYSTEM
BUS SPEED
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
PART NUMBER
MT9LSDT3272(L)AG-13E_
MT9LSDT3272(L)AY-13E_
MT9LSDT3272(L)A(I)G-133_
MT9LSDT3272(L)A(I)Y-133_
MT9LSDT3272(L)AG-10E_
MT9LSDT3272(L)AY-10E_
MT18LSDT6472(L)AG-13E_
MT18LSDT6472(L)AY-13E_
MT18LSDT6472(L)A(I)G-133_
MT18LSDT6472(L)A(I)Y-133_
MT18LSDT6472(L)AG-10E_
MT18LSDT6472(L)AY-10E_
NOTE:
Designators for component and PCB revision are the last two characters of each part number Consult factory for current
revision codes. Example: MT9LSDT3272AG-133B1.
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
Table 4:
Pin Assignment
(168-Pin DIMM Front)
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
CKE1
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
NC
SDA
SCL
V
DD
Table 5:
Pin Assignment
(168-Pin DIMM Back)
106
CB5
127
V
SS
148
107
V
SS
128 CKE0
149
108
NC
129
S3#
150
109
NC
130 DQMB6
151
110
V
DD
131 DQMB7 152
111 CAS# 132
NC
153
154
112 DQMB4 133
V
DD
113 DQMB5 134
NC
155
114
S1#
135
NC
156
115 RAS# 136
CB6
157
116
V
SS
137
CB7
158
117
A1
138
V
SS
159
118
A3
139 DQ48 160
119
A5
140 DQ49 161
120
A7
141 DQ50
162
121
A9
142 DQ51
163
122
BA0
143
V
DD
164
123
A11
144 DQ52
165
124
V
DD
145
NC
166
125
CK1
146
NC
167
126
A12
147
NC
168
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
Figure 2: Pin Locations (168-Pin DIMM)
Front View
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
PIN 1
PIN 41
PIN 84
Back View
U11
U12
U13
(Populated only for 512MB)
U14
U15
U16
U17
U18
U19
PIN 168
Indicates a V
DD
pin
PIN125
Indicates a V
SS
pin
PIN 85
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
Table 6:
Pin Descriptions
SYMBOL
RAS#, CAS#,
WE#
CK0–CK3
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in
progress). CKE is synchronous except after the device enters
power- down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto prcharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory arrary in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Check Bits. ECC, 1-bit error detection and correction.
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS
27, 111, 115
42, 79, 125, 163
63, 128
CKE0, CKE1
Input
30, 45,114, 129
S0#–S3#
Input
28, 29, 46, 47, 112, 113, 130,
131
DQMB0–DQMB7
Input
39, 122
BA0, BA1
Input
33–38, 117–121, 123, 126
A0–A12
Input
83
165–167
21, 22, 52, 53, 105, 106, 136,
137
2–5, 7–11, 13–17, 19, 20,
55–58, 60, 65–67, 69–72, 74–
77, 86–89, 91–95, 97–101,
103, 104,139–142, 144,
149–151, 153–156,158–161
82
SCL
SA0–SA2
CB0–CB7
DQ0–DQ63
Input
Input
Input/
Output
Input/ Data I/O: Data bus.
Output
SDA
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-
detect portion of the module.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
4
256MB (x72, ECC, SR), 512MB (x72, ECC, DR)
168-PIN SDRAM UDIMM
Table 6:
Pin Descriptions
SYMBOL
V
DD
TYPE
Supply
DESCRIPTION
Power Supply: +3.3V ±0.3V.
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS
6, 18, 26, 40, 41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127, 138,
148, 152, 162
24, 25, 31, 44, 48, 50, 51 61,
62, 80, 81, 108, 109, 132, 134,
135, 145,146, 147
V
SS
Supply
Ground.
NC
–
Not Connected: These pins are not connected on these
module.
09005aef807b3709
SD9_18C32_64X72AG.fm - Rev. E 11/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
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