256MB, 512MB, 1GB (x72, ECC, SR) 168-PIN SDRAM RDIMM
Features
Synchronous DRAM Module
MT18LSDT3272 – 256MB
MT18LSDT6472 – 512MB
MT18LSDT12872 – 1GB
For the latest data sheet, please refer to the Micron
Web site:
www.micron.com/products/modules
Features
• 168-pin, PC100- and PC133-compliantm dual in-
line memory module (DIMM)
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Utilizes 125 MHz and 133 MHz SDRAM components
• Supports ECC error detection and correction
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB
(128 Meg x 72)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of PLL clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, Includes Concurrent Auto Precharge
• Auto Refresh Mode
• Self Refresh Mode: 64ms, 4,096-cycle refresh
(256MB); 8,192 cycle refresh (512MB, 1GB)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1:
Timing Parameters
CL = CAS (READ) latency
Module
Marking
-13E
-133
-10E
Clock
Frequency
133 MHz
133 MHz
100 MHz
Access Time
CL = 2
5.4ns
–
9ns
CL = 3
–
5.4ns
7.5ns
Setup
Time
1.5
1.5
2ns
Hold
Time
0.8
0.8
1ns
Figure 1:
168-Pin DIMM (MO-161)
Standard 1.70in. (43.18mm)
Low Profile 1.20in. (30.48mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/CAS Latency
2
133 MHz/CL = 2
133 MHz/CL = 3
100 MHz/CL = 2
• PCB
Standard 1.70in. (43.18mm)
Low Profile 1.20in. (30.48mm)
Marking
G
Y
1
-13E
-133
-10E
1
See page 2 note
See page 2 note
Notes: 1. Contact Micron for product availability.
2. Registered mode adds one clock cycle to CL.
Table 2:
Address Table
Parameter
256MB
4K
4 (BA0, BA1)
128Mb (32 Meg x 4)
4K (A0–A11)
2K (A0–A9, A11)
1 (S0#, S2#)
512MB
8K
4 (BA0, BA1)
256Mb (64 Meg x 4)
8K (A0–A12)
2K (A0–A9, A11)
1 (S0#, S2#)
1GB
8K
4 (BA0, BA1)
512Mb (128 Meg x 4)
8K (A0–A12)
4K (A0–A9, A11, A12)
1 (S0#, S2#)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
PDF: 09005aef809b1694/Source: 09005aef809b15eb
SD18C32_64_128x72G.fm - Rev. C 3/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB (x72, ECC, SR) 168-PIN SDRAM RDIMM
Pin Assignments and Descriptions
Table 3:
Part Numbers
Part Number
Module Density
Configuration
System Bus Speed
256MB
32 Meg x 72
133 MHz
MT18LSDT3272G-13E__
256MB
32 Meg x 72
133 MHz
MT18LSDT3272Y-13E__
256MB
32 Meg x 72
133 MHz
MT18LSDT3272G-133__
256MB
32 Meg x 72
133 MHz
MT18LSDT3272Y-133__
256MB
32 Meg x 72
100 MHz
MT18LSDT3272G-10E__
256MB
32 Meg x 72
100 MHz
MT18LSDT3272Y-10E__
512MB
64 Meg x 72
133 MHz
MT18LSDT6472G-133__
512MB
64 Meg x 72
133 MHz
MT18LSDT6472Y-133__
512MB
64 Meg x 72
133 MHz
MT18LSDT6472G-13E__
512MB
64 Meg x 72
133 MHz
MT18LSDT6472Y-13E__
512MB
64 Meg x 72
100 MHz
MT18LSDT6472G-10E__
512MB
64 Meg x 72
100 MHz
MT18LSDT6472Y-10E__
1GB
128 Meg x 72
133 MHz
MT18LSDT12872G-133__
1GB
128 Meg x 72
133 MHz
MT18LSDT12872Y-133__
1GB
128 Meg x 72
133 MHz
MT18LSDT12872G-13E__
1GB
128 Meg x 72
133 MHz
MT18LSDT12872Y-13E__
1GB
128 Meg x 72
100 MHz
MT18LSDT12872G-10E__
1GB
128 Meg x 72
100 MHz
MT18LSDT12872Y-10E__
Notes: 1. The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT18LSDT6472G-133D2.
Pin Assignments and Descriptions
Table 4:
Pin Assignment (168-Pin DIMM Front)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PDF: 09005aef809b1694/Source: 09005aef809b15eb
SD18C32_64_128x72G.fm - Rev. C 3/05 EN
Symbol
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Symbol
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
Pin
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
DNU
NC
NC
SDA
SCL
V
DD
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 168-PIN SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Pin Assignment (168-Pin DIMM Back)
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Symbol
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
Pin
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
CB5
V
SS
NC
NC
V
DD
CAS#
DQMB4
DQMB5
NC
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
DNU
NC/A12
1
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Symbol
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
Pin
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
DNU
NC
SA0
SA1
SA2
V
DD
Notes: 1. Pin 126 is NC for 256MB , A12 for 512MB and 1GB.
Figure 2:
Front View
U1
U2
168-Pin DIMM Pin Locations
U3
U4
U5
U6
U7
U8
U9
Front View
U12
U1
U2
U3
U4
U5
U11
U6
U7
U8
U9
U10
U11
U12
U14
U10
U14
PIN 1
PIN 41
PIN 84
PIN 1
PIN 41
PIN 84
Back View
U15
U16
U17
U18
U19
U20
U7
U22
U23
Back View
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U24
PIN 168
PIN125
PIN 85
PIN 168
PIN125
PIN 85
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
PDF: 09005aef809b1694/Source: 09005aef809b15eb
SD18C32_64_128x72G.fm - Rev. C 3/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 168-PIN SDRAM RDIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions
Pin numbers are listed in module pinout order; see Pin Assignment tables on page 2 for more information
Pin Numbers
27, 111, 115
42, 79, 125, 163
128
Symbol
WE#, CAS#,
RAS#
CK0–CK3
CKE0
Type
Input
Input
Input
Description
Command Inputs: WE#, CAS#, and RAS# (along with S#) define
the command being entered.
Clock: CK is distributed through an on-board PLL to all devices.
CK1–CK3 are terminated.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides POWER-DOWN and SELF
REFRESH operation (all device banks idle) or CLOCK SUSPEND
operation (burst access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CK, are disabled during
power-down and self refresh modes, providing low standby
power.
Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S#
is registered HIGH. S# is considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input data
is masked when DQMB is sampled HIGH during a WRITE cycle. The
output buffers are placed in a High-Z state (two- clock latency)
when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
Address Inputs: sampled during the ACTIVE command and READ/
WRITE command, with A10 defining auto precharge, to select one
location out of the memory array in the respective device bank.
A10 is sampled during a PRECHARGE command to determine if
both device banks are to precharged (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Register Enable.
Data I/Os: Data bus.
30, 45
S0#, S2#
Input
28–29, 46–47, 112–113,
130–131
DQMB0–
DQMB7
Input
39, 122
BA0, BA1
Input
33–38, 117–121, 123,
126
(512MB, 1GB)
A0–A11
(256MB)
A0–A12
(512MB, 1GB)
Input
83
165–167
147
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95, 97–
101, 103–104, 139–142,
144, 149–151, 153–156,
158–161
21–22, 52–53, 105–106,
136–137
82
SCL
SA0–SA2
REGE
DQ0–DQ63
Input
Input
Input
Input/
Output
CB0–CB7
SDA
6, 18, 26, 40-41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
V
DD
Input/ Check Bits.
Output
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and data out of the presence-
detect portion of the module.
Supply Power Supply: +3.3V ±0.3V.
PDF: 09005aef809b1694/Source: 09005aef809b15eb
SD18C32_64_128x72G.fm - Rev. C 3/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 168-PIN SDRAM RDIMM
Functional Block Diagram
Table 6:
Pin Descriptions (Continued)
Pin numbers are listed in module pinout order; see Pin Assignment tables on page 2 for more information
Pin Numbers
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127,
138, 148, 152, 162
24, 25, 26, 31, 44, 48, 50,
51, 61, 62, 63, 80, 81, 108,
109, 114, 126 (256MB),129,
132, 134, 135, 145, 146, 164
Symbol
V
SS
Type
Supply
Ground.
Description
NC
—
Not Connected: These pins are not connected on these modules.
Functional Block Diagram
All resistor values are 10Ω unless otherwise specified.
Per industry standard, Micron uses various component speed grades as referenced in
the Module Part Numbering Guide at
www.micron.com/support/numbering.html.
Standard modules use the following SDRAM devices: MT48LC32M4A2TG (256MB);
MT48LC64M4A2TG(512MB); MT48LC128M4A2TG (1GB). Lead-free modules use the fol-
lowing SDRAM devices: MT48LC32M4A2P (256MB); MT48LC64M4A2P (512MB);
SMT48LC128M4A2P (1GB).
PDF: 09005aef809b1694/Source: 09005aef809b15eb
SD18C32_64_128x72G.fm - Rev. C 3/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
