128MB, 256MB (x72, ECC, SR): 168-Pin SDRAM RDIMM
Features
SDRAM RDIMM
MT9LSDT1672 – 128MB
MT9LSDT3272 – 256MB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 168-pin, PC133-compliant registered dual in-line
memory module (RDIMM)
• Phase-lock loop (PLL) clock driver to reduce loading
• Uses 133 MHz SDRAM components
• Supports ECC error detection and correction
• 128MB (16 Meg x 72) and 256MB (32 Meg x 72)
• V
DD
= +3.3V
• Fully synchronous; all signals are registered on the
positive edge of the PLL clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full
page
• Single rank
• Auto precharge option
• Auto and self refresh modes: 15.625µs (128MB) or
7.81µs (256MB) maximum periodic refresh interval
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
168-Pin RDIMM (MO-161 R/C A)
Figure 1:
Standard Layout
PCB height: 38.1mm (1.5in)
Figure 2:
Low Profile Layout
PCB height: 28.58mm (1.125in)
Options
Marking
• Package
–
168-pin DIMM
G
–
168-pin DIMM (Pb-free)
Y
1
• Frequency/CAS latency
–
133 MHz/CL = 2
-13E
–
133 MHz/CL = 3
-133
Notes: 1. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1:
Speed
Grade
-13E
-133
Key Timing Parameters
Data Rate (MT/s)
Industry
Nomenclature
PC133
PC133
CL = 2
133
–
CL = 3
–
133
t
RCD
t
RP
t
RC
(ns)
15
20
(ns)
15
20
(ns)
60
66
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C16_32x72.fm - Rev. D 1/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128MB, 256MB (x72, ECC, SR): 168-Pin SDRAM RDIMM
Features
Table 2:
Parameter
Refresh count
Device banks
Device configuration
Row address
Column address
Module ranks
Addressing
128MB
4K
4 (BA0, BA1)
128Mb (16 Meg x 8)
4K (A0–A11)
1K (A0–A9)
1 (S0#, S2#)
256MB
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
1 (S0#, S2#)
Table 3:
Part Numbers and Timing Parameters – 128MB Modules
Base device: MT48LC16M8A2,
1
128Mb SDRAM
Part Number
2
Module
Density
128MB
128MB
128MB
128MB
Configuration
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
Memory Clock/
Data Rate
7.5ns/133 MT/s
7.5ns/133 MT/s
7.5ns/133 MT/s
7.5ns/133 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
2-2-2
2-2-2
3-3-3
3-3-3
MT9LSDT1672G-13E__
3
MT9LSDT1672Y-13E__
3
MT9LSDT1672G-133__
MT9LSDT1672Y-133__
Table 4:
Part Numbers and Timing Parameters – 256MB Modules
Base device: MT48LC32M8A2,
1
256Mb SDRAM
Part Number
2
MT9LSDT3272G-13E__
MT9LSDT3272Y-13E__
MT9LSDT3272G-133__
MT9LSDT3272Y-133__
Notes:
Module
Density
256MB
256MB
256MB
256MB
Configuration
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
Memory Clock/
Data Rate
7.5ns/133 MT/s
7.5ns/133 MT/s
7.5ns/133 MT/s
7.5ns/133 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
2-2-2
2-2-2
3-3-3
3-3-3
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT9LSDT3272G-133D2.
3. End of life.
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C16_32x72.fm - Rev. D 1/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB (x72, ECC, SR): 168-Pin SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Figure 3:
Pin Assignments
168-Pin SDRAM RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
Notes:
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
NF
NC
NC
SDA
SCL
V
DD
168-Pin SDRAM RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
106
107
108
109
110
111
CB5
V
SS
NC
NC
V
DD
CAS#
127
128
129
V
SS
CKE0
NC
148
149
150
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
NF
NC
SA0
SA1
SA2
V
DD
130 DQMB6 151
131 DQMB7 152
132
NC
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
112 DQMB4 133
113 DQMB5 134
114
115
116
117
118
119
120
121
122
123
124
125
NC
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
NF
135
136
137
138
139
140
141
142
143
144
145
146
126 NF/A12
1
147
1. Pin 126 is NF for 128MB and A12 for 256MB.
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C16_32x72.fm - Rev. D 1/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB (x72, ECC, SR): 168-Pin SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Type
Input
Description
Address inputs:
Sampled during the ACTIVE and READ/WRITE commands, with A10
defining auto precharge, to select one location out of the memory array in the
respective device bank. A10 is sampled during a PRECHARGE command to determine
whether both device banks are precharged (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE REGISTER command. A0–A11 (256MB) and
A0–A12 (256MB).
Bank address inputs:
BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock:
CK0 is distributed through an on-board PLL to all devices. CK1–CK3 are
terminated.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) the CK
signal. Deactivating the clock provides power-down and SELF REFRESH operations (all
device banks idle) or CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input buffers,
including CK, are disabled during power-down and self refresh modes, providing low
standby power.
Input/output mask:
DQMB is an input mask signal for write accesses and an output
enable signal for read accesses. Input data is masked when DQMB is sampled HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Register enable.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when S# is registered HIGH. S# is considered part
of the command code.
Presence-detect address inputs:
These pins are used to configure the presence-
detect device.
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect
data transfer to and from the module.
Check bits.
Data input/output:
Data bus.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses
and data into and data out of the EEPROM portion of the module.
Power supply:
+3.3V ±0.3V.
Ground.
Not connected:
These pins are not connected on the module.
No function:
Connected within the module but provides no functionality.
Symbol
A0–A12
BA0, BA1
CK0–CK3
CKE0
Input
Input
Input
DQMB0–DQMB7
Input
RAS#, CAS#, WE#
REGE
S0#, S2#
Input
Input
Input
SA0–SA2
SCL
CB0–CB7
DQ0–DQ63
SDA
V
DD
V
SS
NC
NF
Input
Input
Input/
Output
Input/
Output
Input/
Output
Supply
Supply
–
–
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C16_32x72.fm - Rev. D 1/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved
128MB, 256MB (x72, ECC, SR): 168-Pin SDRAM RDIMM
Functional Block Diagrams
Functional Block Diagrams
Figure 4:
Functional Block Diagram – Standard Layout
RS0#
RDQMB0
RDQMB4
V
SS
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
CS#
DQ
DQ
DQ
U1
DQ
DQ
DQ
DQ
DQ
RDQMB5
DQM
CS#
DQ
DQ
DQ
U2
DQ
DQ
DQ
DQ
DQ
DQM
CS#
DQ
DQ
DQ
DQ
U12
DQ
DQ
DQ
DQ
RDQMB6
V
SS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM
CS#
DQ
DQ
DQ
DQ
U14
DQ
DQ
DQ
DQ
DQM
CS#
DQ
DQ
DQ
DQ
U13
DQ
DQ
DQ
DQ
RDQMB1
V
SS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
V
SS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
V
SS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
RS2#
RDQMB2
V
SS
V
SS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
CS#
DQ
DQ
DQ
DQ
U3
DQ
DQ
DQ
DQ
RDQMB7
DQM
CS#
DQ
DQ
DQ
DQ
U4
DQ
DQ
DQ
DQ
V
SS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
CS#
DQ
DQ
DQ
DQ
U11
DQ
DQ
DQ
DQ
DQM
CS#
DQ
DQ
DQ
DQ
U10
DQ
DQ
DQ
DQ
RDQMB3
V
SS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
V
SS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U5, U7
RAS#
CAS#
CKE0
WE#
A0–A11/A12
BA0
BA1
S0#, S2#
DQMB0–DQMB7
RRAS#:
SDRAM
U6
CK0
PLL
R
e
g
i
s
t
e
r
s
RCAS#:
SDRAM
RCKE0:
SDRAM
RWE#:
SDRAM
RA0–RA11/RA12:
SDRAM
RBA0:
SDRAM
RBA1:
SDRAM
RS0#, RS2#
RDQMB0–RDQMB7
SCL
SDRAM
x 3
SDRAM
x 3
SDRAM
x 3
Register x 2
V
SS
CK1–CK3
U9
SPD
EEPROM
WP A0
A1
A2
V
SS
SDA
V
DD
V
SS
SDRAM
SDRAM
REGE
V
DD
U8
V
SS
SA0 SA1 SA2
PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d
SD9C16_32x72.fm - Rev. D 1/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved
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