MX29GL256E
MX29GL256E DATASHEET
P/N:PM1499
REV. 1.1, JUN. 29, 2009
1
MX29GL256E
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
- MX29GL256E H/L: VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC
- MX29GL256E U/D: VI/O=1.65V~3.6V for Input/Output
• Byte/Word mode switchable
- 33,554,432 x 8 / 16,777,216 x 16
• 64KW/128KB uniform sector architecture
- 256 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security
- Features factory locked and identifiable, and customer lockable
• Advanced sector protection function (Solid and Password Protect)
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ VLKO
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Deep power down mode
PERFORMANCE
• High Performance
- Fast access time:
- MX29GL256E H/L: 100ns (VCC=2.7~3.6V), 90ns (VCC=3.0~3.6V)
- MX29GL256E U/D: 110ns (VCC=2.7~3.6V, V I/O=1.65 to Vcc)
- Page access time:
- MX29GL256E H/L: 25ns
- MX29GL256E U/D: 30ns
- Fast program time: 11us/word
- Fast erase time: 0.6s/sector
• Low Power Consumption
- Low active read current: 30mA (typical) at 5MHz
- Low standby current: 30uA (typical)
• Typical 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
- Suspends sector program operation to read data from another sector which is not being program
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability
PACKAGE
• 56-Pin TSOP
• 64-Ball FBGA (10mm x 13mm)
• 64-Ball LFBGA (11mm x 13mm)
• 70-Pin SSOP
•
All Pb-free devices are RoHS Compliant
P/N:PM1499
REV. 1.1, JUN. 29, 2009
2
MX29GL256E
PIN CONFIGURATION
56 TSOP
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
NC
V
I/O
64 FBGA/64 LFBGA
8
NC
A22
A23
VIO
GND
NC
NC
NC
7
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
Q13
GND
A9
A8
A10
A11
Q7
Q14
Q6
5
WE#
RES-
ET#
WP#/
ACC
A17
A21
A19
Q5
Q12
VCC
Q4
4
RY/
BY#
A7
A18
A20
Q2
Q10
Q11
Q3
3
A6
A5
Q0
Q8
Q9
Q1
2
A3
A4
A2
A1
A0
CE#
OE#
GND
1
NC
NC
NC
NC
NC
VIO
NC
NC
A
B
C
D
E
F
G
H
P/N:PM1499
REV. 1.1, JUN. 29, 2009
3
MX29GL256E
70 SSOP
A20
A21
A18
A17
OE#
A6
A5
A4
A3
A2
A1
A0
BYTE#
GND
NC
NC
NC
NC
NC
NC
GND
NC
CE#
GND
NC
A7
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
NC
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
A19
A8
A15
A10
A11
A12
A13
A14
A9
A16
WE#
NC
A22
A23
GND
NC
NC
WP#/ACC
NC
NC
NC
GND
RESET#
GND
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A23
Q0~Q14
Q15/A-1
CE#
WE#
OE#
RESET#
WP#/ACC*
RY/BY#
BYTE#
VCC
GND
NC
VI/O
Address Input
Data Inputs/Outputs
Q15(Word Mode)/LSB addr(Byte Mode)
Chip Enable Input
Write Enable Input
Output Enable Input
Hardware Reset Pin, Active Low
Hardware Write Protect/Programming
Acceleration input
Read/Busy Output
Selects 8 bits or 16 bits mode
+3.0V single power supply
Device Ground
Pin Not Connected Internally
Power Supply for Input/Output
LOGIC SYMBOL
24
A0-A23
Q0-Q15
(A-1)
16 or 8
CE#
OE#
WE#
RESET#
WP#/ACC
BYTE#
VI/O
RY/BY#
Notes:
1. WP#/ACC has internal pull up.
2. VI/O voltage must tight with VCC.
VI/O = VCC =2.7V~3.6V.
P/N:PM1499
REV. 1.1, JUN. 29, 2009
4
MX29GL256E
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
CONTROL
INPUT
LOGIC
WRITE
PROGRAM/ERASE
HIGH VOLTAGE
STATE
MACHINE
(WSM)
STATE
FLASH
ARRAY
ARRAY
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
REGISTER
X-DECODER
ADDRESS
LATCH
A0-AM
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
P/N:PM1499
REV. 1.1, JUN. 29, 2009
5
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
