512MB, 1GB (x72, SR) 244-Pin DDR2 Mini-RDIMM
Features
DDR2 SDRAM Mini-RDIMM
MT9HTF6472PKY – 512MB
MT9HTF12872PKY – 1GB
Features
•
244-pin, mini registered dual in-line memory
module
•
Fast data transfer rates: PC2-6400, PC2-5300,
PC2-4200, or PC2-3200
•
512MB (64 Meg x 72) or 1GB (128 Meg x 72)
•
Supports ECC error detection and correction
•
Single rank
•
V
DD
= V
DDQ
= 1.8V
•
V
DDSPD
= 1.7–3.6V
•
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
•
Differential data strobe (DQS, DQS#) option
•
4n-bit prefetch architecture
•
DLL to align DQ and DQS transitions with CK
•
Multiple internal device banks for concurrent
operation
•
Programmable CAS latency (CL)
•
Posted CAS additive latency (AL)
•
WRITE latency = READ latency - 1
t
CK
•
Programmable burst lengths: 4 or 8
•
Adjustable data-output drive strength
•
64ms, 8192-cycle refresh
•
On-die termination (ODT)
•
Serial presence-detect (SPD) with EEPROM
•
Gold edge contacts
•
Lead-free
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
800
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
553
553
400
CL = 3
400
400
400
400
400
t
RCD
t
RP
t
RC
Figure 1: 244-Pin Mini-RDIMM (MO-244 R/C A)
Module height: 30mm (1.18in)
Options
•
Parity
•
Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (-40°C
≤
T
A
≤
+85°C)
1
•
Package
–
244-pin DIMM (lead-free)
•
Frequency/CL
2
–
2.5ns @ CL = 5 (DDR2-800)
–
2.5ns @ CL = 6 (DDR2-800)
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
3
Notes:
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not recommended for future designs.
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef817ab1fc
htf9c64_128x72pky.pdf - Rev. E 3/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, SR) 244-Pin DDR2 Mini-RDIMM
Features
Table 2: Addressing
512MB
Refresh count
Row addressing
Device bank addressing
Device configuration
Column addressing
Module rank addressing
8K
16K A[13:0]
4 BA[1:0]
512Mb (64 Meg x 8)
1K A[9:0]
1 S0#
1GB
8K
16K A[13:0]
8 BA[2:0]
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
Table 3: Part Numbers and Timing Parameters – 512MB
Base device: MT47H64M8,
1
512Mb DDR2 SDRAM
Module
Part Number
2
Density
Configuration
MT9HTF6472PK(I)Y-80E__
MT9HTF6472PK(I)Y-800__
MT9HTF6472PK(I)Y-667__
MT9HTF6472PK(I)Y-53E__
MT9HTF6472PK(I)Y-40E__
512MB
512MB
512MB
512MB
512MB
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Table 4: Part Numbers and Timing Parameters – 1GB
Base device: MT47H128M8,
1
1Gb DDR2 SDRAM
Module
2
Part Number
Density
Configuration
MT9HTF12872PK(I)Y-80E__
MT9HVF12872PK(I)Y-800__
MT9HVF12872PK(I)Y-667__
MT9HVF12872PK(I)Y-53E__
MT9HVF12872PK(I)Y-40E__
Notes:
1GB
1GB
1GB
1GB
1GB
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Clock Cycles
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
sult factory for current revision codes. Example: MT9HTF12872KY-667A2.
PDF: 09005aef817ab1fc
htf9c64_128x72pky.pdf - Rev. E 3/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, SR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments
Pin Assignments
Table 5: Pin Assignments
244-Pin MiniDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
57
58
59
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
V
DDQ
CKE0
V
DD
NC/BA2
1
V
DDQ
A11
A7
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
88
89
90
V
DDQ
A2
V
DD
V
SS
V
SS
Par_In
V
DD
A10/AP
BA0
V
DD
WE#
V
DDQ
CAS#
V
DDQ
NC
NC
V
DDQ
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0/
RDQS0
244-Pin MiniDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
154
155
156
157
158
DQ28
DQ29
V
SS
DM3/
RDQS3
185
186
187
188
A3
A1
V
DD
CK0
CK0#
V
DD
A0
BA1
V
DD
RAS#
V
DDQ
S0#
V
DDQ
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4/
RDQS4
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
NF/
RDQS5#
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6/
RDQS6
NF/
RDQS6#
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/
RDQS7
NF/
RDQS7#
V
SS
DQ62
DQ63
V
SS
SDA
SCL
NC/
189
RDQS3#
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/
RDQS8
190
191
192
193
194
195
196
197
NF/
159
RDQS0#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/
RDQS1
160
161
162
163
164
165
166
167
NC/
198
RDQS8#
V
SS
CB6
CB7
V
SS
NC
V
DDQ
NC
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
199
200
201
202
203
204
205
206
207
208
209
210
211
212
NF/
168
RDQS1#
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/
RDQS2
169
170
171
172
173
174
175
176
177
178
179
NF/
238
RDQS4#
V
SS
DQ38
DQ39
V
SS
DQ44
239
240
241
242
243
56 Err_Out# 87
NF/
180
RDQS2#
V
SS
181
PDF: 09005aef817ab1fc
htf9c64_128x72pky.pdf - Rev. E 3/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, SR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments
Table 5: Pin Assignments (Continued)
244-Pin MiniDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
29
30
31
V
SS
DQ18
DQ19
60
61
62
V
DD
A5
A4
Note:
91
92
93
DQ40
DQ41
V
SS
122
SA1
151
152
153
DQ22
DQ23
V
SS
244-Pin MiniDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
182
183
184
A8
A6
V
DDQ
213
214
215
DQ45
V
SS
DM5/
RDQS5
244
V
DDSPD
1. Pin 55 is NC for 512MB, or BA2 for 1GB.
PDF: 09005aef817ab1fc
htf9c64_128x72pky.pdf - Rev. E 3/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, SR) 244-Pin DDR2 Mini-RDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only):
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination:
Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
Used to configure the SPD EEPROM address range on the I
2
C
bus.
Serial clock for SPD EEPROM:
Used to synchronize communication to and from the
SPD EEPROM on the I
2
C bus.
Check bits.
Used for system error detection and correction.
Data input/output:
Bidirectional data bus.
Data strobe:
Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
BAx
Input
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
PDF: 09005aef817ab1fc
htf9c64_128x72pky.pdf - Rev. E 3/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2005 Micron Technology, Inc. All rights reserved.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
