4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM
Features
DDR3 SDRAM SODIMM
MT16JSS51264HY – 4GB
Features
•
DDR3 functionality and operations supported as de-
fined in the component data sheet
•
204-pin, small-outline dual in-line memory module
(SODIMM)
•
Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
•
4GB (512 Meg x 64)
•
V
DD
= 1.5V ±0.075V
•
V
DDSPD
= +3.0V to +3.6V
•
Nominal and dynamic on-die termination (ODT) for
data and strobe mask signals
•
Dual rank, using 4Gb TwinDie™ DRAM
•
On-board I
2
C temperature sensor with integrated se-
rial presence-detect (SPD) EEPROM
•
Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
•
Selectable BC4 or BL8 on-the-fly (OTF)
•
Gold edge contacts
•
Lead-free
•
Fly-by topology
•
Terminated control, command, and address bus
Table 1: Key Timing Parameters
Speed
Grade
-1G6
-1G4
-1G1
-1G0
-80B
Industry
Nomenclature
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
Data Rate (MT/s)
CL = 11 CL = 10
1600
–
–
–
–
1333
1333
–
–
–
CL = 9
1333
1333
–
–
–
CL = 8
1066
1066
1066
1066
–
CL = 7
1066
1066
1066
–
–
CL = 6
800
800
800
800
800
CL = 5
667
667
667
667
667
t
RCD
t
RP
t
RC
Figure 1: 204-Pin SODIMM (MO-268 R/C D)
Module height: 30.0mm (1.18in)
Options
•
Operating
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
•
Package
–
204-pin DIMM (lead-free)
•
Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
Note:
temperature
1
Marking
None
I
Y
-1G6
-1G4
-1G1
1. Contact Micron for industrial temperature
module offerings.
(ns)
13.125
13.125
13.125
15
15
(ns)
13.125
13.125
13.125
15
15
(ns)
48.125
49.125
50.625
52.5
52.5
PDF: 09005aef832ed836
jss16c512x64hy.pdf – Rev. D 3/11
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
4GB
8K
32K A[14:0]
8 BA[2:0]
4Gb TwinDie (512 Meg x 8)
1K A[9:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41J512M8THU,
1
4Gb TwinDie DDR3 SDRAM
Module
2
Part Number
Density
Configuration
MT16JSS51264H(I)Y-1G6__
MT16JSS51264H(I)Y-1G4__
MT16JSS51264H(I)Y-1G1__
Notes:
4GB
4GB
4GB
512 Meg x 64
512 Meg x 64
512 Meg x 64
Module Band-
width
12.8 GB/s
10.6 GB/s
8.5 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
sult factory for current revision codes. Example: MT16JSS51264HY-1G1D1.
PDF: 09005aef832ed836
jss16c512x64hy.pdf – Rev. D 3/11
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
204-Pin DDR3 SODIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DM0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
CK0#
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
A13
S1#
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
–
–
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
–
–
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
V
SS
DQ4
DQ5
V
SS
DQS0#
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
RESET#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
V
SS
DQ22
DQ23
204-Pin DDR3 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
A14
V
DD
A11
A7
V
DD
A6
A4
V
DD
A2
A0
V
DD
CK1
CK1#
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
V
DD
BA1
RAS#
V
DD
S0#
ODT0
V
DD
ODT1
NC
V
DD
V
REFCA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
200
202
204
–
–
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SDA
SCL
V
TT
–
–
198 EVENT#
PDF: 09005aef832ed836
jss16c512x64hy.pdf – Rev. D 3/11
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 5: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
Clock:
Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Data mask (x8 devices only):
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination:
Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-
ized as though a normal power-up was executed.
Chip select:
Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
Used to configure the temperature sensor/SPD EEPROM ad-
dress range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
Used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM on the I
2
C bus.
Check bits:
Used for system error detection and correction.
Data input/output:
Bidirectional data bus.
Data strobe:
Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
BAx
Input
CKx,
CKx#
CKEx
DMx
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
Input
Input
Input
(LVCMOS)
Input
Input
Input
I/O
I/O
I/O
Sx#
SAx
SCL
CBx
DQx
DQSx,
DQSx#
PDF: 09005aef832ed836
jss16c512x64hy.pdf – Rev. D 3/11
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
4GB (x64, DR): 204-Pin DDR3 SDRAM SODIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
SDA
TDQSx,
TDQSx#
Type
I/O
Output
Description
Serial data:
Used to transfer addresses and data into and out of the temperature sensor/
SPD EEPROM on the I
2
C bus.
Redundant data strobe (x8 devices only):
TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
EVENT#
V
DD
V
DDSPD
V
REFCA
V
REFDQ
V
SS
V
TT
NC
NF
Output
Parity error output:
Parity error found on the command and address bus.
(open drain)
Output
Temperature event:The
EVENT# pin is asserted by the temperature sensor when crit-
(open drain) ical temperature thresholds have been exceeded.
Supply
Supply
Supply
Supply
Supply
Supply
–
–
Power supply:
1.5V ±0.075V. The component V
DD
and V
DDQ
are connected to the mod-
ule V
DD
.
Temperature sensor/SPD EEPROM power supply:
3.0–3.6V.
Reference voltage:
Control, command, and address V
DD
/2.
Reference voltage:
DQ, DM V
DD
/2.
Ground.
Termination voltage:
Used for control, command, and address V
DD
/2.
No connect:
These pins are not connected on the module.
No function:
These pins are connected within the module, but provide no functionality.
PDF: 09005aef832ed836
jss16c512x64hy.pdf – Rev. D 3/11
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2008 Micron Technology, Inc. All rights reserved.
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