ICS87993I
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
PLL C
LOCK
D
RIVER W
/D
YNAMIC
C
LOCK
S
WITCH
G
ENERAL
D
ESCRIPTION
The ICS87993I is a PLL clock driver designed specifically
for redundant clock tree designs. The device receives two
differential LVPECL clock signals from which it generates
5 new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signal frequency and phase
while the other three pairs generate 2x, phase aligned clock
outputs. External PLL feedback is used to also provide zero
delay buffer performance.
The ICS87993I Dynamic Clock Switch (DCS) circuit
continuously monitors both input CLK signals. Upon
detection of a failure (CLK stuck HIGH or LOW for at least 1
period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the DCS will switch to the good
secondary clock and phase/frequency alignment will
occur with minimal output phase disturbance. The typical
phase bump caused by a failed clock is eliminated.
F
EATURES
•
5 differential 3.3V LVPECL outputs
•
Selectable differential clock inputs
•
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Output frequency range: 50MHz to 250MHz
•
VCO range: 200MHz to 500MHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Cycle-to-cycle jitter (RMS): 20ps (maximum)
•
Output skew: 70ps (maximum), within one bank
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package available
P
IN
A
SSIGNMENT
nQB0
nQB1
nQB2
QB0
QB1
QB2
V
CC
24 23 22 21 20 19 18 17
nQA1
QA1
nQA0
QA0
V
CC
V
CCA
MAN_OVERRIDE
PLL_SEL
25
26
27
28
29
30
31
32
1
nMR
V
CC
16
V
CC
INP0BAD
INP1BAD
CLK_SELECTED
V
EE
nEXT_FB
EXT_FB
V
EE
ICS87993I
32-Lead QFP (LQFP)
7mm x 7mm x 1.4mm
package body
Y Package
Top View
2
nALARM_RESET
15
14
13
12
11
10
9
B
LOCK
D
IAGRAM
PLL_SEL
CLK_SELECTED
INP1BAD
INP0BAD
MAN_OVERRIDE
ALARM_RESET
SEL_CLK
nCLK0
CLK0
nCLK1
CLK1
nEXT_FB
EXT_FB
nMR
87993AYI
3
CLK0
4
nCLK0
5
CLK_SEL
6
CLK1
7
nCLK1
8
V
EE
Dynamic Switch
Logic
nQB0
QB0
nQB1
QB1
÷2
PLL
÷4
nQB2
QB2
nQA0
QA0
nQA1
QA1
www.idt.com
1
REV. C JULY 26, 2010
ICS87993I
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
PLL C
LOCK
D
RIVER W
/D
YNAMIC
C
LOCK
S
WITCH
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
Name
nMR
Input
Type
Description
Active LOW Master Reset. When logic LOW, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs
Pullup
nQx to go high. When logic HIGH, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
When LOW, resets the input bad flags and aligns CLK_SELECTED
Pullup
with SEL_CLK. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
2
3
4
5
6
7
8, 9, 12
10
11
13
14
nALARM_RESET
CLK0
nCLK0
SEL_CLK
CLK1
nCLK1
V
EE
EXT_FB
nEXT_FB
CLK_SELECTED
INP1BAD
Input
Input
Input
Input
Input
Input
Power
Input
Input
Output
Output
Inver ting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0 inputs. When
Pulldown
HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Negative supply pins.
Pulldown Differential external feedback.
Pullup
Differential external feedback.
LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1
is selected. LVCMOS / LVTTL interface levels.
Indicates detection of a bad input reference clock 1 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until
the alarm reset is asser ted.
Indicates detection of a bad input reference clock 0 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until
the alarm reset is asser ted.
Core supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
Manual override. When HIGH, disables internal clock switch circuitr y.
Pulldown
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.When HIGH, selects PLL.
Pullup
LVCMOS / LVTTL interface levels.
15
16, 17,
24, 29
18, 19
20, 21
22, 23
25, 26
2 7, 28
30
31
32
INP0BAD
V
CC
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
V
CCA
MAN_OVERRIDE
PLL_SEL
Output
Power
Output
Output
Output
Output
Output
Power
Input
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
87993AYI
www.idt.com
2
REV. C JULY 26, 2010
ICS87993I
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
PLL C
LOCK
D
RIVER W
/D
YNAMIC
C
LOCK
S
WITCH
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
80
15
Maximum
3.465
3.465
180
20
Units
V
V
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
LVCMOS Inputs
LVCMOS Inputs
SEL_CLK,
MAN_OVERRIDE
Input High Current
nALARM_RESET,
PLL_SEL, nMR
SEL_CLK,
MAN_OVERRIDE
Input Low Current
nALARM_RESET,
PLL_SEL, nMR
Output High Voltage; NOTE 1
Test Conditions
Minimum
2
-0.3
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-120
2.4
0.5
Typical
Maximum
3.3
0.8
5
120
Units
V
V
µA
µA
µA
µA
V
V
I
IL
V
OH
V
OL
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
CC
/2. See Parameter Measurement Information Section,
"3.3V Output Load AC Test Circuit diagram".
T
ABLE
3C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
Parameter
CLK0, CLK1,
EXT_FB
Input High Current
nCLK0, nCLK1,
nEXT_FB
CLK0, CLK1,
EXT_FB
Input Low Current
nCLK0, nCLK1,
nEXT_FB
Peak-to-Peak Input Voltage
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-120
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
120
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended appliations, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
87993AYI
www.idt.com
3
REV. C JULY 26, 2010
ICS87993I
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
PLL C
LOCK
D
RIVER W
/D
YNAMIC
C
LOCK
S
WITCH
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
VCO
t
PWI
CLKx to Q
t
PD
Propagation Delay
CLKx to EXT_FB;
NOTE 2
PLL_SEL = LOW
PLL_SEL = HIGH
fVCO
≤
360MHz
PLL_SEL = HIGH
fVCO
≤
500MHz
20% to 80% @ 50MHz
Parameter
PLL VCO Lock Range
Test Conditions
Minimum Typical
200
25
2.8
-150
-150
200
3.45
0
0
Maximum
500
75
4.1
170
200
800
70
100
20
Tested at
typical conditions
10
200
100
f
≤
360MHz
45
50
25
400
200
55
20
10
Units
MHz
%
ns
ps
ps
ps
ps
ps
ps/cycle
ps/cycle
ps/cycle
ps/cycle
%
ps
ms
t
R /
t
F
Output Rise Time
Output Skew;
NOTE 3
Within Bank
All Outputs
75MHz Output;
NOTE 1, 4
150MHz Output;
NOTE 1, 4
75MHz Output;
NOTE 1, 5
150MHz Output;
NOTE 1, 5
t
sk(o)
Δ
PER/CYCLE
Rate of change
of Periods
odc
Output Duty Cycle
Cycle-to-Cycle Jitter (RMS); NOTE 1
PLL Lock Time; NOTE 1
t
jit(cc)
t
L
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: These parameters are guaranteed by characterization. Not tested in production.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Specification holds for a clock switch between two signals no greater than 400ps out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
NOTE 5: Specification holds for a clock switch between two signals no greater than ±
π
out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
87993AYI
www.idt.com
4
REV. C JULY 26, 2010
ICS87993I
1-
TO
-5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
PLL C
LOCK
D
RIVER W
/D
YNAMIC
C
LOCK
S
WITCH
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CC
V
CC
,
V
CCA
Qx
SCOPE
nCLK0,
nCLK1
V
PP
LVPECL
nQx
Cross Points
V
CMR
V
EE
CLK0,
CLK1
V
EE
-1.3V ± 0.165V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
nQy
Qy
nQAx,
nQBx
nQAx,
nQBx
t
cycle
n
➤
t
sk(o)
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
O
UTPUT
S
KEW
C
YCLE
-
TO
-C
YCLE
J
ITTER
80%
Clock
Outputs
80%
V
SW I N G
nQAx,
nQBx
nQAx,
nQBx
Pulse Width
t
PERIOD
20%
t
R
t
F
20%
odc =
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
87993AYI
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
www.idt.com
5
REV. C JULY 26, 2010
➤
➤
t
cycle n+1
➤
PCB设计
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