FemtoClock
®
NG Universal Frequency
Translator
Description
The 8T49N241 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with one
integer and three fractional output dividers, allowing the generation of
up to four different output frequencies, ranging from 8kHz to 1GHz.
These frequencies are completely independent of each other, the
input reference frequencies, and the crystal reference frequency. The
device places virtually no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error. The outputs may select among LVPECL, LVDS, HCSL or
LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N241 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N241 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I
2
C interface. It also supports
I
2
C master capability to allow the register configuration to be read
from an external EEPROM.
Programming with IDT’s
Timing Commander
software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
8T49N241
Datasheet
Typical Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• One integer divider ranging from ÷4 to ÷786,420
• Three fractional output dividers (see
Output Dividers)
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I
2
C or via external I
2
C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40-VFQFPN, lead-free (RoHS 6)
©2019 Integrated Device Technology, Inc.
1
March 5, 2019
8T49N241 Datasheet
8T49N241 Block Diagram
CLK0
P0
CLK1
P1
Input Clock
Monitoring,
Priority,
&
Selection
IntN Divider
FracN
Feedback
PLL
FracN Divider
Q0
Q1
XTAL
OSC
FracN Divider
Reset
Logic
FracN Divider
OTP
I
2
C Slave
Status &
Control
Registers
GPIO
Logic
4
Q2
nRST
Q3
I
2
C Master
SCLK
SDATA
Serial EEPROM
nWP
S_A[1:0]
GPIO
nINT
Figure 1. 8T49N241 Block Diagram
©2019 Integrated Device Technology, Inc.
2
March 5, 2019
8T49N241 Datasheet
Pin Assignment
GPIO[3]
GPIO[2]
V
CCO3
30 29 28 27 26 25 24 23 22 21
V
CCO2
nINT
V
CCA
nQ3
nQ2
Q3
Q2
nRST
V
CCA
OSCI
OSCO
nWP
V
CCCS
CAP
CAP_REF
V
CCA
S_A0
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
20
19
18
17
S_A1
nCLK1
CLK1
nCLK0
CLK0
V
CC
V
EE
V
CC
SCLK
SDATA
8T49N241
16
15
14
13
12
11
GPIO[0]
GPIO[1]
V
CCA
V
CCA
Q0
nQ0
V
CCO0
nQ1
40-pin 6mm x 6mm VFQFPN
Figure 2. 8T49N242 Pin Assignments
©2019 Integrated Device Technology, Inc.
V
CCO1
Q1
3
March 5, 2019
8T49N241 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Name
V
CCA
V
CCA
GPIO[0]
V
CCO0
Q0
nQ0
GPIO[1]
nQ1
Q1
V
CCO1
SDATA
SCLK
V
CC
V
EE
V
CC
CLK0
nCLK0
CLK1
nCLK1
S_A1
V
CCO2
Q2
nQ2
GPIO[2]
nQ3
Q3
V
CCO3
GPIO[3]
nINT
Power
Power
I/O
Power
O
O
I/O
O
O
Power
I/O
I/O
Power
Power
Power
I
I
I
I
I
Power
O
O
I/O
O
O
Power
I/O
O
Pullup
Universal
Universal
Pullup
Universal
Universal
Pulldown
Pullup /
Pulldown
Pulldown
Pullup /
Pulldown
Pulldown
Pullup
Pullup
Universal
Universal
Pullup
Universal
Universal
Pullup
Type
1
Description
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Analog function supply for analog functions associated with the PLL. 2.5V or 3.3V
supported.
General-purpose input-output. LVTTL / LVCMOS Input levels.
High-speed output supply for output pair Q0, nQ0. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
Output Clock 0. Please refer to the
Output Drivers
for more details.
Output Clock 0. Please refer to the
Output Drivers
for more details.
General-purpose input-output. LVTTL / LVCMOS Input levels.
Output Clock 1. Please refer to the
Output Drivers
for more details.
Output Clock 1. Please refer to the
Output Drivers
for more details.
High-speed output supply for output pair Q1, nQ1. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
I
2
C interface bi-directional data.
I
2
C interface bi-directional clock.
Core digital function supply. 2.5V or 3.3V supported.
Negative supply voltage. All V
EE
pins and EPAD must be connected before any
positive supply voltage is applied.
Core digital function supply. 2.5V or 3.3V supported.
Non-inverting differential clock input 0.
Inverting differential clock input 0.
V
CC
/ 2 when left floating (set by internal pullup / pulldown resistors)
Non-inverting differential clock input 1.
Inverting differential clock input 1.
V
CC
/ 2 when left floating (set by internal pullup / pulldown resistors).
I
2
C Address Bit A1
High-speed output supply voltage for output pair Q2, nQ2. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
Output Clock 2. Please refer to the
Output Drivers
for more details.
Output Clock 2. Please refer to the
Output Drivers
for more details.
General-purpose input-output. LVTTL / LVCMOS Input levels.
Output Clock 3. Please refer to the
Output Drivers
for more details.
Output Clock 3. Please refer to the
Output Drivers
for more details.
High-speed output supply voltage for output pair Q3, nQ3. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
General-purpose input-output. LVTTL / LVCMOS Input levels.
Open-drain
Interrupt output.
with pullup
©2019 Integrated Device Technology, Inc.
4
March 5, 2019
8T49N241 Datasheet
Number
30
Name
V
CCA
Power
Type
1
Description
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
Pullup
Master Reset input. LVTTL / LVCMOS interface levels:
0 = All registers and state machines are reset to their default values
1 = Device runs normally
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Crystal Input. Accepts a 10MHz – 50MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal. For proper device
functionality, a crystal or external oscillator must be connected to this pin.
Crystal Output. This pin must be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
Pullup
Write Protect input. LVTTL / LVCMOS interface levels.
0 = Write operations on the serial port will complete normally, but will have no
effect except on interrupt registers.
Output supply for Control & Status pins:
GPIO[3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST
1.8V, 2.5V or 3.3V supported
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
31
32
33
nRST
V
CCA
OSCI
I
Power
I
34
OSCO
O
35
nWP
I
36
V
CCCS
Power
37
38
39
40
ePAD
CAP
CAP_REF
V
CCA
S_A0
Exposed Pad
Analog
Analog
Power
I
Power
Pulldown
I
2
C Address Bit A0.
Negative supply voltage. All V
EE
pins and ePAD must be connected before any
positive supply voltage is applied.
NOTE 1:
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
©2019 Integrated Device Technology, Inc.
5
March 5, 2019
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
