MR16R0828DR(T)0
(8Mx16)*8pcs Consumer RIMM
Module based on 128Mb D-die, 32s banks,16K/32ms Ref, 2.5V
Overview
The Consumer RIMM
module is a general purpose high-
performance memory module suitable for use in a broad
range of applications including computer memory, personal
computers, workstations and other applications where high
bandwidth and low latency are required.
The Consumer RIMM module consists of 128Mb RDRAM
devices of consumer package. These are extremely high-
speed CMOS DRAMs organized as 8M words by 16 bits.
The use of Rambus Signaling Level (RSL) technology
permits to 800 MHz transfer rates while using conventional
system and board design technologies. RDRAM devices are
capable of sustained data transfers at 1.25ns per two bytes
(10ns per 16 bytes).
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM device's 32-bank architecture
supports up to four simultaneous transactions per device.
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available for Consumer RIMM modules.
Table 1: Part Number by Freq. & Latency
Speed
Organization
Bin
I/O
Freq.
(MHz)
800
800
t
RAC
(Row
Access
Time) ns
40
40
Part Number
64M x 16
64M x 16
-CM8
-CM8
MR16R0828DR
a
0-CM8
MR16R0828DT
b
0-CM8
a. WBGA leaded for Consumer Package
b. WBGA lead- free for consumer Package
Form Factor
The Consumer RIMM modules are offered in 184-pad 1mm
edge connector pad pitch suitable for 184 contact Consumer
RIMM connectors. Figure 1 below, shows a eight device
Consumer RIMM module.
Features
♦
High speed 800MHz RDRAM storage
♦
184 edge connector pads with 1mm pad spacing
♦
Module PCB size : 133.35mm x 31.75mm x 1.27mm
(5.25” x 1.25” x 0.05”)
♦
Each RDRAM device has 32 banks, for a total of 256
banks on each 128MB module respectively
♦
Gold plated edge connector pad contacts
♦
Serial Presence Detect(SPD) support
♦
Operates from a 2.5 volt supply (±5%)
♦
Powerdown self refresh modes
♦
Separate Row and Column buses for higher efficiency
♦
WBGA consumer package(54 Balls)
Note: There is only single side type for Consumer RIMM module
Figure 1: Consumer RIMM Module shown with heat spreader removed
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Version 1.0 July 2002
MR16R0828DR(T)0
Signal
Pins
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
B10
B12
B34
A20, B20, A22, B22, A24
A14
A12
B2, A4, B4, A6, B6, A8, B8, A10
A32, B30, A30, B28, A28, B26, A26,
B24
B16, A18, B18
A34
A2, A16, B14, A38, B32, B38, A40,
B40, A43, B43, A44, B44, A45, B45,
A46, B46, A47, B47, A48, B48, A49,
B49, A50, B50, B61, A77, B79, A91
B83
B81
B59
A73, B73, A71, B71, A69
I
I
I
I
RSL
RSL
V
CMOS
RSL
I
I
I
I
I
I
I/O
I/O
I
I
RSL
RSL
V
CMOS
RSL
RSL
RSL
RSL
RSL
RSL
V
CMOS
I/O
Type
Description
Gnd
Ground reference for RDRAM core and interface. 72 PCB
connector pads.
LCFM
LCFMN
LCMD
LCOL4..
LCOL0
LCTM
LCTMN
LDQA7..
LDQA0
LDQB7..
LDQB0
LROW2..
LROW0
LSCK
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command used to read from and write to the control
registers. Also used for power management.
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
Data bus A. A 8-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device.
Data bus B. A8-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device.
Row bus. 3-bit bus containing control and address information
for row accesses.
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
These pads are not connected. These 28 connector pads are
reserved for future use.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command Input. Pin used to read from and write to the
control registers. Also used for power management.
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
NC
RCFM
RCFMN
RCMD
RCOL4..
RCOL0
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Version 1.0 July 2002
MR16R0828DR(T)0
Signal
RCTM
RCTMN
RDQA7..
RDQA0
RDQB7..
RDQB0
RROW2..
RROW0
RSCK
SA0
SA1
SA2
SCL
SDA
SIN
SOUT
SV
DD
SWP
V
CMOS
Vdd
Vref
A79
A81
B91, A89, B89, A87, B87, A85, B85,
A83
A61, B63, A63, B65, A65, B67, A67,
B69
B77, A75, B75
A59
B53
B55
B57
A53
A55
B36
A36
A56, B56
A57
A35, B35, A37, B37
A41, A42, A54, A58, B41, B42, B54,
B58
A51, B51
I
SV
DD
Pins
I/O
I
I
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
Type
RSL
RSL
RSL
RSL
RSL
V
CMOS
SV
DD
SV
DD
SV
DD
SV
DD
SV
DD
V
CMOS
V
CMOS
Description
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
Data bus A. A 8-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device.
Data bus B. A 8-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device.
Row bus. 3-bit bus containing control and address information
for row accesses.
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
Serial Presence Detect Data (Open Collector I/O).
Serial I/O for reading from and writing to the control registers.
Attaches to SIO0 of the first RDRAM device on the module.
Serial I/O for reading from and writing to the control registers.
Attaches to SIO1 of the last RDRAM device on the module.
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1
and SA2.
Serial Presence Detect Write Protect (active high). When low,
the SPD can be written as well as read.
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
Supply voltage for the RDRAM core and interface logic.
Logic threshold reference voltage for RSL signals.
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Version 1.0 July 2002
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