Datasheet> 器件分类 > 存储> 存储> 5962D122042QXC

文档预览

5962D122042QXC: 产品描述Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48; 产品类别存储存储; 文件大小994KB，共44页; 制造商Cobham Semiconductor Solutions

下载文档详细参数选型对比全文预览

5962D122042QXC概述

Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48

5962D122042QXC规格参数

参数名称	属性值
厂商名称	Cobham Semiconductor Solutions
零件包装代码	DFP
包装说明	DFP,
针数	48
Reach Compliance Code	unknown
ECCN代码	3A001.A.2.C
最长访问时间	60 ns
备用内存宽度	8
启动块	BOTTOM/TOP
JESD-30 代码	R-CDFP-F48
JESD-609代码	e4
长度	16 mm
内存密度	67108864 bit
内存集成电路类型	FLASH
内存宽度	16
功能数量	1
端子数量	48
字数	4194304 words
字数代码	4000000
工作模式	ASYNCHRONOUS
组织	4MX16
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	DFP
封装形状	RECTANGULAR
封装形式	FLATPACK
并行/串行	PARALLEL
编程电压	3.3 V
认证状态	Not Qualified
筛选级别	MIL-PRF-38535 Class Q
座面最大高度	3.05 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
端子面层	GOLD
端子形式	FLAT
端子节距	0.635 mm
端子位置	DUAL
总剂量	10k Rad(Si) V
类型	NOR TYPE
宽度	9.65 mm
最长写入周期时间 (tWC)	60 ms

5962D122042QXC文档预览

Standard Products

UT8QNF8M8 64Mbit NOR Flash Memory

Advanced Data Sheet

December 16, 2011

FEATURES



64Mbits organized as either 8M x 8-bits or 4M x16-bits



Fast 60ns read/write access time



Functionally compatible with traditional single power

supply Flash devices



Simultaneous read/write operations



Flexible bank architecture



Single 3.3V power supply



Ultra low power consumption



Near zero power standby operation



Full HiRel temperature range (-55

C to 105



Data retention > 20 years @55

Programming Endurance: 10k cycles per sector

48-pin ceramic flatpack package

Operational environment:

- Total dose: 10, 30 or 50 krad(Si)

- SEL Immune: 80 MeV-cm

/mg @ 85

- SEU Immune: Memory Cell 100 MeV-cm

/mg @25



Standard Microelectronic Drawing (SMD), 5962-12204

- QML Q and Q+ pending

INTRODUCTION

The Aeroflex 64Mbit, 3.3 volt-only flash memory device, can

be organized as 4,194,304 words of 16-bits each or 8,388,608

bytes of 8-bits each. Word mode data appears on DQ[15:0];

byte mode data appears on DQ[7:0]. The device is designed to

be programmed in-system with the standard 3.3 volt VCC

supply and can also be programmed in standard PROM

programmers. The device is available with an access time of

60 ns and is offered in a 48-pin ceramic flatpack package.

Standard control pins—Chip Enable (CE#), Write Enable

(WE#), and Output Enable (OE#)—control normal read and

write operations, and avoid bus contention issues. The device

operates from a single 3.3 volt power supply.

APPLICATION

The UT8QNF8M8 64Mbit Flash Memory is compatible for use

with the UT699 LEON 3FT microprocessor. In a typical

application, the microprocessor transfers an image of the

application program or kernel from non-volatile memory, such

as flash, to volatile memory, such as SRAM. The Aeroflex

64Mbit NOR Flash is intended to provide customers with a non-

volatile solution that has a memory capacity large enough to

house a typical application program or kernel.

Figure 1. UT8QNF8M8 Flash Block Diagram

48-Lead Flatpack

Top View

A15

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

A21

WP#

RY/BY#

A18

A17

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

Table 1. Pin Descriptions

SIGNAL

A[21:0]

DQ[14:0]

DQ15/A-1

CE#

OE#

WE#

WP#

RESET#

BYTE#

RY/BY#

22 Address pins

15 Data Inputs/Outputs, (x16-mode only)

DQ15 (Data Input/Output, word mode), A-1 (LSB

Address Input, byte mode)

Chip Enable, Active Low

Output Enable, Active Low

Write Enable, Active Low

Hardware Write Protect

Hardware reset pin, Active Low

Select 8-bit or 16-bit mode, Active Low

Ready/Busy Output, Active Low

3.3 volt only single power supply (see supply

tolerances)

Device Ground

FUNCTION

Figure 2. UT8QNF8M8 Pinout (48)

SIMULTANEOUS READ/WRITE OPERATIONS WITH

ZERO LATENCY

The Simultaneous Read/Write architecture provides simultane-

ous operation by dividing the memory space into four banks, two

8 Mb banks with small and large sectors, and two 24 Mb banks

of large sectors. Sector addresses are fixed, system software can

be used to form user-defined bank groups.

During an Erase/Program operation, any of the three non-busy

banks may be read from. Note that only two banks can operate

simultaneously. The device can improve overall system perfor-

mance by allowing a host system to program or erase in one

bank, then immediately and simultaneously read from the other

bank, with zero latency. This releases the system from waiting

for the completion of program or erase operations.

The UT8QNF8M8 is organized as a dual boot device with both

top and bottom boot sectors.

Table 2. Bank Architecture

Bank 1

Bank 2

Bank 3

Bank 4

8 Mb

24 Mb

8 Mb

Eight 8 kbyte/4 kword,

Fifteen 64 kybte/32 word

Forty-eight 64 kbyte/32 kword

Eight 8 kbyte/4 kword,

Fifteen 64 kbyte/32 kword

UT8QNF8M8 FEATURES

The device offers complete compatibility with the JEDEC 42.4

single-power-supply Flash command set standard. Commands

are written to the command register using standard micropro-

cessor write timings. Reading data out of the device is similar

to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase opera-

tion is complete by using the device status bits: RY/BY# pin,

DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a pro-

gram or erase cycle has been completed, the device automati-

cally returns to the read mode.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data contents of

other sectors. The device is fully erased when shipped from the

factory.

Hardware data protection measures include a low VCC detector

that automatically inhibits write operations during power tran-

sitions. The hardware sector protection feature disables both

program and erase operations in any combination of the sectors

of memory.

The Erase Suspend/Erase Resume feature enables the user to

put erase on hold for any period of time to read data from, or

program data to, any sector that is not selected for erasure. True

background erase can thus be achieved.

The device offers two power-saving features. When addresses

have been stable for a specified amount of time, the device en-

ters the automatic sleep mode. The system can also place the

deviceinto the standby mode. Power consumption is greatly re-

duced in both modes.

DEVICE BUS OPERATION

This section describes the requirements and use of the device

bus operations, which are initiated through the internal

command register. The command register itself does not

occupy any addressable memory location. The register is a

latch used to store the commands, along with the address and

data information needed to execute the command. The

contents of the register serve as inputs to the internal state

machine. The state machine outputs dictate the function of

the device. Table 3 lists the device bus operations, the inputs

and control levels they require, and the resulting output.

Table 3. UT8QNF8M8 Device Bus Operations

DQ[15:8]

OPERATION

Read

Write

Standby

Output Disable

Reset

CE#

0.3V

OE#

RESET#

0.3V

WP#

L/H

(Note 2)

L/H

Addresses

BYTE#

= V

OUT

High-Z

BYTE# = V

DQ[14:8] = High-Z,

DQ15 = A-1

High-Z

DQ[7:0]

OUT

High-Z

Notes:

1. Addresses are A21:A0 in word mode (BYTE# = VIH), A21:A-1 in byte mode (BYTE# = VIL).

2. If WP# = VIL, sectors 0, 1, 140, and 141 remain protected. If WP# = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last

protected or unprotected.

查看更多（仅显示前5页内容，查看全部内容请下载文档。）>

5962D122042QXC相似产品对比

	5962D122042QXC	5962D122041QXC	5962R122042QXC	5962R122041QXC	5962P122041QXC	5962P122042QXC	UT8QNF8M8-60XCC
描述	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48	Flash, 4MX16, 60ns, CDFP48, CERAMIC, DFP-48
厂商名称	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions	Cobham Semiconductor Solutions
零件包装代码	DFP	DFP	DFP	DFP	DFP	DFP	DFP
包装说明	DFP,	DFP,	DFP,	DFP,	DFP,	DFP,	CERAMIC, DFP-48
针数	48	48	48	48	48	48	48
Reach Compliance Code	unknown	unknown	unknown	unknown	unknow	unknow	unknow
ECCN代码	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A991.B.1.A
最长访问时间	60 ns	60 ns	60 ns	60 ns	60 ns	60 ns	60 ns
备用内存宽度	8	8	8	8	8	8	8
启动块	BOTTOM/TOP	BOTTOM/TOP	BOTTOM/TOP	BOTTOM/TOP	BOTTOM/TOP	BOTTOM/TOP	BOTTOM/TOP
JESD-30 代码	R-CDFP-F48	R-CDFP-F48	R-CDFP-F48	R-CDFP-F48	R-CDFP-F48	R-CDFP-F48	R-CDFP-F48
JESD-609代码	e4	e4	e4	e4	e4	e4	e4
长度	16 mm	16 mm	16 mm	16 mm	16 mm	16 mm	16 mm
内存密度	67108864 bit	67108864 bit	67108864 bit	67108864 bit	67108864 bi	67108864 bi	67108864 bi
内存集成电路类型	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
内存宽度	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1
端子数量	48	48	48	48	48	48	48
字数	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words
字数代码	4000000	4000000	4000000	4000000	4000000	4000000	4000000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
组织	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	DFP	DFP	DFP	DFP	DFP	DFP	DFP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK	FLATPACK
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
编程电压	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
座面最大高度	3.05 mm	3.05 mm	3.05 mm	3.05 mm	3.05 mm	3.05 mm	3.05 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子面层	GOLD	GOLD	GOLD	GOLD	GOLD	GOLD	GOLD
端子形式	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT	FLAT
端子节距	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
类型	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
宽度	9.65 mm	9.65 mm	9.65 mm	9.65 mm	9.65 mm	9.65 mm	9.65 mm
最长写入周期时间 (tWC)	60 ms	60 ms	60 ms	60 ms	60 ms	60 ms	60 ms
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
筛选级别	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	-
总剂量	10k Rad(Si) V	10k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	30k Rad(Si) V	30k Rad(Si) V	-

5962D122042QXC

5962D122042QXC概述

5962D122042QXC规格参数

5962D122042QXC文档预览

5962D122042QXC相似产品对比

推荐资源