INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT137
3-to-8 line decoder/demultiplexer
with address latches; inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
FEATURES
•
Combines 3-to-8 decoder with 3-bit latch
•
Multiple input enable for easy expansion or independent
controls
•
Active LOW mutually exclusive outputs
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT137 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT137
The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (A
n
). The “137”
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “137” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.
The output enable input (E
1
and E
2
) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E
1
is LOW and E
2
is HIGH.
The “137” is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
A
n
to Y
n
LE to Y
n
E
1
to Y
n
E
2
to Y
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
18
17
15
15
3.5
57
19
21
17
15
3.5
59
ns
ns
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
PIN DESCRIPTION
PIN NO.
1, 2, 3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
SYMBOL
A
0
to A
2
LE
E
1
E
2
GND
Y
0
to Y
7
V
CC
NAME AND FUNCTION
data inputs
latch enable input (active LOW)
data enable input (active LOW)
data enable input (active HIGH)
ground (0 V)
multiplexer outputs
positive supply voltage
74HC/HCT137
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
December 1990
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
min. typ.
t
PHL
/ t
PLH
propagation delay
A
n
to Yn
propagation delay
LE to Y
n
propagation delay
E
1
to Y
n
propagation delay
E
2
to Y
n
output transition time
50
10
9
50
10
9
30
6
5
58
21
17
55
20
16
50
18
14
50
18
14
19
7
6
11
4
3
3
1
1
3
1
1
max.
180
36
31
190
38
32
145
29
25
145
29
25
75
15
13
65
13
11
65
13
11
40
8
7
−40
to
+85
min. max.
225
45
38
240
48
41
180
36
31
180
36
31
95
19
16
75
15
13
75
15
13
45
9
8
−40
to
+125
min.
max.
270
54
46
285
57
48
220
44
38
220
44
38
110
22
19
ns
74HC/HCT137
TEST CONDITIONS
UNIT
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
/ t
PLH
ns
Fig.6
t
THL
/ t
TLH
ns
Fig.6
t
W
LE pulse width
HIGH
set-up time
A
n
to LE
hold time
A
n
to LE
ns
Fig.8
t
su
ns
Fig.8
t
h
ns
Fig.8
December 1990
5
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