Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
(x16) MCP ComboMemories
Preliminary Specifications
FEATURES:
• ComboMemories organized as:
– SST32HF324x: 2M x16 Flash + 256K x16 SRAM
– SST32HF328x: 2M x16 Flash + 512K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current:
- SST32HF32x: 80 µA (typical)
- SST32HF32xC: 25 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Fast Read Access Times:
– Flash: 70 ns and 90 ns
– SRAM: 70 ns and 90 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
– Chip Rewrite Time:
SST32HF32x/32xC: 15 seconds (typical)
• Flash Automatic Erase and Program Timing
– Internal V
PP
Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 63-ball TFBGA (8mm x 10mm x 1.2mm)
– 63-ball LFBGA (8mm x 10mm x 1.4mm)
– 62-ball LFBGA (8mm x 10mm x 1.4mm)
PRODUCT DESCRIPTION
The SST32HF32x/32xC ComboMemory devices integrate
a 2M x16 CMOS flash memory bank with a 256K x16 or
512K x16 CMOS SRAM memory bank in a Multi-Chip
Package (MCP), manufactured with SST’s proprietary, high
performance SuperFlash technology. The SST32HF32x
devices use a Pseudo-SRAM. The SST32HF32xC devices
use standard SRAM.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 15 seconds for the
SST32HF32x/32xC, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion of
Program operation. To protect against inadvertent flash
write, the SST32HF32x/32xC devices contain on-chip
hardware and software data protection schemes. The
SST32HF32x/32xC devices offer a guaranteed endurance
of 10,000 cycles. Data retention is rated at greater than
100 years.
The SST32HF32x/32xC devices consist of two indepen-
dent memory banks with respective bank enable signals.
The Flash and SRAM memory banks are superimposed in
the same memory address space. Both memory banks
©2003 Silicon Storage Technology, Inc.
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1
share common address lines, data lines, WE# and OE#.
The memory bank selection is done by memory bank
enable signals. The memory bank selection is done by two
bank enable signals. The SRAM bank enable signals,
BES1# and BES2, select the SRAM bank. The flash mem-
ory bank enable signal, BEF#, has to be used with Soft-
ware Data Protection (SDP) command sequence when
controlling the Erase and Program operations in the flash
memory bank.
The SST32HF32x/32xC provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
MPF (Multi-Purpose Flash) and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
The SST32HF32x/32xC devices are suited for applications
that use both flash memory and SRAM memory to store
code or data. For systems requiring low power and small
form factor, the SST32HF32x/32xC devices significantly
improve performance and reliability, while lowering power
consumption, when compared with multiple chip solutions.
The SST32HF32x/32xC inherently use less energy during
erase and program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Concurrent Read/Write Operation
The SST32HF32x/32xC provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. See Figure 23 for a flowchart. The following
table lists all valid states.
C
ONCURRENT
R
EAD
/W
RITE
S
TATES
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read
The Read operation of the SST32HF32x/32xC devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when OE# is high. Refer to Figure 6 for
further details.
Device Operation
The SST32HF32x/32xC use BES1#, BES2 and BEF# to
control operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time.
If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to V
IHC
(Logic High) or
when BEF# is high and BES2 is low.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
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Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Flash Word-Program Operation
The flash memory bank of the SST32HF32x/32xC devices
is programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
operation consists of three steps. The first step is the three-
byte load sequence for Software Data Protection. The sec-
ond step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed, within 10
µs. See Figures 7 and 8 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 19 for flow-
charts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. Any SDP commands loaded during the
internal Program operation will be ignored.
Flash Chip-Erase Operation
The SST32HF32x/32xC provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 22 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
Flash Write Operation Status Detection
The SST32HF32x/32xC provide one hardware and two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
Write cycle time. The software detection includes two
status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE#, which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling
(DQ
7
) or Toggle Bit (DQ
6
) Read may be simultaneous with
the completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
7
or DQ
6
. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF32x/32xC offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A
20
-A
11
are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A
20
-A
15
are used to determine the block
address. The sector or block address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The End-of-Erase operation can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figures 12 and 13 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
3
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Flash Data# Polling (DQ
7
)
When the SST32HF32x/32xC flash memory banks are in
the internal Program operation, any attempt to read DQ
7
will produce the complement of the true data. Once the
Program operation is completed, DQ
7
will produce true
data. Note that even though DQ
7
may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ
7
will pro-
duce a ‘0’. Once the internal Erase operation is completed,
DQ
7
will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 9 for Data# Polling timing diagram and Figure
20 for a flowchart.
Flash Software Data Protection (SDP)
The SST32HF32x/32xC provide the JEDEC approved
software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF32x/32xC devices are shipped with the software
data protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode, within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or
V
IH,
but no other value, during any SDP command
sequence.
Concurrent Read and Write Operations
Flash Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
Sector- or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 10 for
Toggle Bit timing diagram and Figure 20 for a flowchart.
The SST32HF32x/32xC provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. The following table lists all valid states.
C
ONCURRENT
R
EAD
/W
RITE
S
TATES
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
Flash Memory Data Protection
The SST32HF32x/32xC flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
4
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Product Identification
The Product Identification mode identifies the devices as
the SST32HFxxx and manufacturer as SST.
This mode
may be accessed by software operations only. The
hardware device ID Read operation, which is typically
used by programmers, cannot be used on this device
because of the shared lines between flash and SRAM
in the multi-chip package. Therefore, application of
high voltage to pin A
9
may damage this device.
Users
may use the software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 14 for the
software ID entry and read timing diagram and Figure 21
for the ID entry command sequence flowchart.
TABLE 1: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST32HF32x/32xC
0001H
2783H
T1.0 1230
SRAM Read
The SRAM Read operation of the SST32HF32x/32xC is
controlled by OE# and BES1#, both have to be low with
WE# and BES2 high for the system to obtain data from the
outputs. BES1# and BES2 are used for SRAM bank selec-
tion. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing diagram,
Figure 3, for further details.
SRAM Write
The SRAM Write operation of the SST32HF32x/32xC is
controlled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 4 and 5, for further details.
Data
00BFH
0000H
Design Considerations
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. This command may
also be used to reset the device to Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g. not read correctly. See
Table 4 for software command codes, Figure 15 for timing
waveform, and Figure 21 for the Software ID Entry com-
mand sequence flowchart.
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between V
DD
and
V
SS
, e.g., less than 1 cm away from the V
DD
pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from V
DD
to V
SS
should be placed within 1 cm of
the V
DD
pin.
SRAM Operation
With BES1# low, BES2 and BEF# high, the
SST32HF32x/32xC operate as either 256K x16 or 512K
x16 CMOS SRAM, with fully static operation requiring no
external clocks or timing strobes. The SST32HF32x/32xC
SRAM is mapped into the first 512 KWord address
space. When BES1#, BEF# are high and BES2 is low, all
memory banks are deselected and the device enters
standby. Read and Write cycle times are equal. The con-
trol signals UBS# and LBS# provide access to the upper
data byte and lower data byte. See Table 3 for SRAM
Read and Write data byte control modes of operation.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
5
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