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SN74CBTLV3245
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034F – JULY 1997 – REVISED MAY 1998
D
D
D
D
D
Standard ’245-Type Pinout
5-Ω Switch Connection Between Two Ports
Isolation Under Power-Off Conditions
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Shrink
Small-Outline (DB), Thin Very Small-Outline
(DGV), Small-Outline (DW), and Thin Shrink
Small-Outline (PW) Packages
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
description
The SN74CBTLV3245 provides eight bits of
high-speed bus switching in a standard ’245
device pinout. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
NC
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
NC – No internal connection
The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on and
port A is connected to port B. When OE is high, the switch is open and a high-impedance state exists between
the two ports.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
OE
L
H
FUNCTION
A port = B port
Disconnect
logic diagram (positive logic)
2
A1
SW
18
B1
9
A8
SW
11
B8
19
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
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1
SN74CBTLV3245
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034F – JULY 1997 – REVISED MAY 1998
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I/O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
VCC
VIH
VIL
Supply voltage
High level control input voltage
High-level
Low-level
Low level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
2.3
1.7
2
0.7
0.8
MAX
3.6
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
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SN74CBTLV3245
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034F – JULY 1997 – REVISED MAY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
Ioff
ICC
∆I
CC‡
Ci
Control inputs
Control inputs
VCC = 3 V,
VCC = 3.6 V,
VCC = 0,
VCC = 3.6 V,
VCC = 3.6 V,
VI = 3 V or 0
VO = 3 V or 0,
VCC = 2.3 V,
23V
2.5
TYP at VCC = 2 5 V
ron§
VCC = 3 V
TEST CONDITIONS
II = –18 mA
VI = VCC or GND
VI or VO = 0 to 3.6 V
IO = 0,
One input at 3 V,
OE = VCC
VI = 0
VI = 1.7 V,
VI = 0
II = 64 mA
II = 24 mA
II = 15 mA
II = 64 mA
II = 24 mA
II = 15 mA
VI = VCC or GND
Other inputs at VCC or GND
3.5
8
¶
¶
¶
5
5
¶
¶
¶
7
7
Ω
MIN
TYP†
MAX
–0.8
±50
30
20
750
UNIT
V
µA
µA
µA
µA
pF
pF
Cio(OFF)
VI = 2.4 V,
10
15
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
¶ This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
tpd#
ten
tdis
FROM
(INPUT)
A or B
OE
OE
TO
(OUTPUT)
B or A
A or B
A or B
¶
¶
VCC = 2.5 V
±
0.2 V
MIN
MAX
¶
¶
¶
VCC = 3.3 V
±
0.3 V
MIN
MAX
0.25
1
1
5.6
6.5
ns
ns
ns
UNIT
¶ This information was not available at the time of publication.
# The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
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3
SN74CBTLV3245
LOW-VOLTAGE OCTAL FET BUS SWITCH
SCDS034F – JULY 1997 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V
±
0.2 V
2
×
VCC
From Output
Under Test
CL = 30 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
Output
Control
(low-level
enabling)
tPZL
VCC
Input
VCC/2
tPLH
VCC/2
0V
tPHL
VOH
Output
VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
tPZH
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
GND
VCC
VCC/2
VCC/2
0V
tPLZ
VCC
VCC/2
VOL + 0.15 V
VOL
tPHZ
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOAD CIRCUIT
VCC/2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω,
tr
≤
2 ns, tf
≤
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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