88E3015/88E3018 Datasheet
Integrated 10/100 Fast Ethernet Transceiver
Doc. No. MV-S103657-00, Rev. C
October 26, 2006
Document Status
Advance
Information
Preliminary
Information
Final
Information
Advance
This document contains design specifications for initial product development. Specifications may
change without notice. Contact Marvell Field Application Engineers for more information.
This document contains preliminary data, and a revision of this document will be published at a
later date. Specifications may change without notice. Contact Marvell Field Application Engineers
for more information.
This document contains specifications on a product that is in final release. Specifications may
change without notice. Contact Marvell Field Application Engineers for more information.
Technical Publication: 1.30
Revision Code: Rev. C
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Doc. No. MV-S103657-00, Rev. C
Page 2
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2006 Marvell
October 26, 2006, Advance
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
O
VERVIEW
The Marvell
®
88E3015/88E3018 devices are the fourth
generation Marvell
®
DSP-based physical layer trans-
ceivers for Fast Ethernet applications. The devices con-
tain all the active circuitry to convert data streams to
and from a Media Access Controller (MAC) and the
physical media. The 88E3015/88E3018 devices incor-
porate IEEE 802.3u Auto-Negotiation in support of both
100BASE-TX and 10BASE-T networks over twisted-
pair cable in full-duplex or half-duplex mode.
The 88E3015/88E3018 devices both support the
Reduced Gigabit Media Independent Interface (RGMII),
and the Media Independent Interface (MII).
The 88E3015/88E3018 devices feature a mode of oper-
ation supporting IEEE compliant 100BASE-FX fiber-
optic networks. Additionally, the 88E3015/88E3018
devices implement Far-End Fault Indication (FEFI) in
order to provide a mechanism for transferring informa-
tion from the local station to the link partner that indi-
cates a remote fault has occurred in 100BASE-FX
mode.
The 88E3015/88E3018 devices feature the Marvell Vir-
tual Cable Tester
®
(VCT™) technology, which enables
IT managers and networking equipment manufacturers
to remotely analyze the quality and characteristics of
the attached cable plant.
The 88E3015/88E3018 devices use advanced mixed-
signal processing and power management techniques
for extremely low power dissipation and high port count
system integration. The 88E3015/88E3018 devices are
manufactured in an all CMOS process.
F
EATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEEE 802.3 compliant 100BASE-TX and 10BASE-
T ports
Reduced Gigabit Media Independent Interface
(RGMII)
Media Independent Interface (MII) support
Source Synchronous MII support
Virtual Cable Tester
®
(VCT™) Technology
PECL interface supporting 100BASE-FX applica-
tions
Automatic MDI/MDIX crossover for 10BASE-T and
100BASE-TX
Jumbo frame support to 10 Kbytes with up to
±
150 ppm clock frequency difference
IEEE 802.3u Auto-Negotiation support for auto-
matic speed and duplex selection
Far-End Fault Indication (FEFI) support for
100BASE-FX applications
Supports 802.3ah Unidirectional Enable
Energy detect feature
Baseline wander correction
Auto-Calibration for MAC Interface outputs
COMA Mode support
Flexible serial management interface (MDC/MDIO)
for register access
Programmable interrupt to minimize polling
IEEE 1149.1 Standard Test Access Port and
boundary scan compatible (88E3018 only)
Supports three (3) LEDs per port
0.15
μm
standard digital CMOS process
56-pin QFN 8 mm x 8 mm package (88E3015
device)
64-pin QFN 9 mm x 9 mm package (88E3018
device)
Available in Industrial grade (88E3018 device,
RoHS 6/6 package only)
88E3015/88E3018 S
PECIFIC
F
EATURES
The 88E3018 device, housed in a 64-pin QFN package,
offers a pin-upgradeable path toward future Gigabit
Ethernet PHY designs. The 88E3018 device includes
support for IEEE 1149.1 JTAG Standard Test Access
Port and Boundary Scan. The 88E3108 device is avail-
able in Industrial grade (RoHS 6/6 compliant package
only)
The 88E3015 device, housed in a 56-pin QFN package,
provides a cost-efficient, increased board savings
option to the 88E3018.
Copyright © 2006 Marvell
October 26, 2006, Advance
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S103657-00, Rev. C
Page 3
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
MDIP/N[0]
MDIP/N[1]
Auto MDIX
Crossover
FX Link
& Auto
Negotiation
DAC
10/100
Transmit
PCS
RGMII
or MII
10/100
Receive
PCS
VREF
CRS
COL
TXD[3:0]
TX_CTRL
TX_CLK
RXD[3:0]
RX_CTRL
RX_CLK
RX_ER
Management
Interface
LED/
Configuration
MDC
MDIO
LED[2:0]
CONFIG[3:0]
SIGDET
10 Mbps
Receiver
ADC
Digital
Adaptive
Equalizer
XTAL_IN
XTAL_OUT
RESETn
COMAn
Clock/
Reset
Baseline
Wander
Canceller
CTRL25
2.5V
Regulator
1.2V
Regulator
DIS_REG12
88E3015 Device Functional Block Diagram
Boundary
Scan
10/100
Mbps
Transmit
PCS
10/100
Mbps
Receive
PCS
RGMII
or MII
VREF
CRS
COL
TXD[3:0]
TX_CTRL
TX_CLK
RXD[3:0]
RX_CTRL
RX_CLK
RX_ER
JTAG
DAC
MDIP/N[0]
MDIP/N[1]
Auto MDIX
Crossover
10 Mbps
Receiver
ADC
Digital
Adaptive
Equalizer
SIGDET
FX Link
& Auto
Negotiation
XTAL_IN
XTAL_OUT
RESETn
COMAn
Clock/
Reset
Baseline
Wander
Canceller
Management
Interface
LED/
Configuration
MDC
MDIO
LED[2:0]
CONFIG[3:0]
CTRL25
2.5V
Regulator
1.2V
Regulator
DIS_REG12
88E3018 Device Functional Block Diagram
Table 1:
88E3015/88E3018 Devices Feature Differences
88E30 15
8 8E301 8
64-pin QFN
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS 6/6 Package Only
Package
MII
RGMII
Virtual Cable Tester
®
Fiber Support
Parallel LEDs
Power Management
JTAG Support
Industrial Grade
56-pin QFN
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Doc. No. MV-S103657-00, Rev. C
Page 4
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2006 Marvell
October 26, 2006, Advance
Table of Contents
S
ECTION
1.
1.1
1.2
1.3
S
IGNAL
D
ESCRIPTION
................................................................... 9
88E3015 Device 56-Pin QFN Pinout ............................................................................. 9
88E3018 Device 64-Pin QFN Pinout ........................................................................... 10
Pin Description ............................................................................................................ 11
1.3.1
1.3.2
1.3.3
Pin Type Definitions .......................................................................................................... 11
88E3015 56-Pin QFN Assignments - Alphabetical by Signal Name................................. 21
88E3018 64-Pin QFN Assignments - Alphabetical by Signal Name................................. 22
S
ECTION
2.
2.1
2.1.1
2.1.2
2.1.3
F
UNCTIONAL
D
ESCRIPTION
......................................................... 23
MAC Interface............................................................................................................... 24
Reduced Gigabit Media Independent Interface (RGMII)................................................... 24
Media Independent Interface (MII).................................................................................... 25
Source Synchronous MII................................................................................................... 26
MDC/MDIO Read and Write Operations........................................................................... 27
Preamble Suppression...................................................................................................... 28
Programming Interrupts ....................................................................................................28
Transmit Side Network Interface....................................................................................... 29
Encoder............................................................................................................................. 29
Receive Side Network Interface........................................................................................ 29
Decoder ............................................................................................................................ 30
Auto-Negotiation ............................................................................................................... 31
IEEE Power Down Mode .................................................................................................. 32
Energy Detect +TM........................................................................................................... 32
Normal 10/100 Mbps Operation........................................................................................ 32
COMA Mode ..................................................................................................................... 33
AVDD ................................................................................................................................ 34
AVDDC ............................................................................................................................. 34
AVDDR ............................................................................................................................. 34
AVDDX.............................................................................................................................. 35
DVDD................................................................................................................................ 35
VDDO................................................................................................................................ 35
VDDOR ............................................................................................................................. 35
2.2
Serial Management Interface ...................................................................................... 27
2.2.1
2.2.2
2.2.3
2.3
Transmit and Receive Functions ............................................................................... 29
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4
Power Management ..................................................................................................... 32
2.4.1
2.4.2
2.4.3
2.4.4
2.5
Regulators and Power Supplies................................................................................. 34
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
Hardware Configuration.............................................................................................. 36
Copyright © 2006 Marvell
October 26, 2006, Advance
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S103657-00, Rev. C
Page 5
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