Converting Designs Using the
LXT385 to the IDT82V2058
Application Note, Jan, 2002 (Ver 3.1)
File No. IDT82V2058AN_01
1.
General description
The IDT82V2058 is a full featured octal E1 line interface unit and is a pin compatible, functional superset
of the Intel (previously Level One) LXT385, octal E1 LIU. Both devices provide the same register
mapping and functions during normal operation. In addition, the IDT82V2058 offers an expanded register
bank to allow increased flexibility and functionality when using a host controller. Converting designs
using the LXT385 to the IDT82V2058 is a straightforward process involving minimal hardware changes.
Software adjustments need only be made in applications where it is intended to access the enhanced
register set of the IDT device. The primary purpose of this application note is to describe the differences
between the LXT385 and the IDT82V2058 and highlight the design considerations that come into play
when converting an existing LXT385 design.
2.
Registers
The register sets of the IDT82V2058 can be divided into Primary Registers and Expanded Registers. The
Primary Registers of the IDT82V2058 are the same as those of the LXT385, with an added ADDP
(Address Pointer) register. The address of the ADDP register in the IDT device is 1F (Hex), which is a
reserved address in the LXT385. Writing "AA Hex" to this register will switch to the Expanded Registers
of the IDT82V2058. (Table 1 shows the Registers in the LXT385 and the Primary Registers in the
IDT82V2058).
The functions controlled by the Expanded Registers are available only with the IDT device as the LXT385
does not offer these registers. Thus, when using only the Primary Registers, the two devices are completely
software compatible but to take advantage of IDT’s additional features and flexibility some software must
be added to source code written for the LXT385. Table 2 shows the Expanded Registers of the
IDT82V2058. Writing "00 Hex" to the "Address Pointer " register will switch back to Primary Registers.
1) Primary Registers:
Address (Hex)
00 -15
16 - 1E
1F
LXT385
Registers
Reserved
Reserved
IDT82V2058
Primary Registers
Reserved
ADDP (Address Pointer), write
"AA Hex" to this register will
switch to Expanded Registers.
Table 1 – Primary Registers IDT82V2058/LXT385
2) Expanded Register:
Address (Hex)
00
01
02
03
04
05
06
07
08 - 1E
1F
Register Name
e-SING (Single Rail Mode Setting)
e-CODE (Encoder/Decoder Selection)
e-CRS (Clock Recovery Enable/Disable)
e-RPDN (Receiver
n
Power Down Enable/Disable)
e-TPDN (Transmitter
n
Power Down Enable/Disable)
e-CZER (Consecutive Zero Detect Enable/Disable)
e-CODV (Code Violation Detect Enable/Disable)
e-EQUA (Equalizer Enable/Disable)
Registers for testing. Default is 0, users should not change the default value
ADDP, writing "00 Hex" to this register will switch to Primary Registers
Table 2 – Enhanced Registers IDT82V2058
3. Working Without MCLK
When MCLK is not available (High/Low), the Receive Path of the IDT82V2058 is the same as the
LXT385, but the Transmit Path is different. For the IDT82V2058, if MCLK is not available, TCLK1 will
be internally used as a virtual MCLK for the Transmit Path (The status of the Receive Path is still
determined by the real MCLK pin). As a result, similar operation can be achieved without an MCLK
signal but, in this case, care must be taken to always supply TCLK1 for normal operation. If neither
MCLK nor TCLK1 is available, the IDT82V2058 will put all the TTIPn and TRINGn pins into high
impedance states. These operation modes are tabulated below.
MCLK
TCLKn
(n=0-7 for Lxt384);
(n=0,2-7 for 2048)
H
Operation Mode of the Transmit Path
LXT385
IDT82V2058
Transmit pulse-shaping is
disabled.
TCLK1 is clocked
TCLK1 is H/L
H/L
Clocked
Transmit with pulse-shaping
TCLK1 is clocked
TCLK1 is H/L
Transmit all ones.
Transmit is high
impedance
Transmit with
pulse-shaping
Transmit is high
impedance.
H/L
Table -3 MCLK and TCLK
4.
External Components
The transmit impedance on the line side between IDT82V2058 and LXT385 is slightly different. When
converting an LXT385 design to the IDT82V2058, the performance will be better if the external transmit
resisters and capacitor are modified. The recommended application circuit for the IDT82V2058 is shown in
Figure-4. It is the same as that of the LXT385, except that the value of R
T
is 9.5 Ohm + 1%. The LXT385
datasheet recommends an R
T
value of 11 Ohm + 1%. In addition, the recommended value of C
P
is 560 pF
for the LXT385, whereas IDT recommends using a C
P value
that is tuned to the line condition.
2:1
• •
R
X
Line
0.22µF
•
•
1kΩ
R
R
R
R
RTIPn
One of Eight Identical
Channels
•
2:1
• •
T
X
Line
C
P
RRINGn
·
TTIPn
IDT82V2058
1kΩ
VDDT
D4
R
T
D3
VDDT
D2
VDDT
VDDDn
0.1µF
GNDTn
•
•
68µF
R
T
·
TRINGn
D1
Component
R
T
C
T
R
R
Rx Transformer
Turns Ratio
Figure 4 – Termination Network
LXT385
IDT82V2058
75Ω Coax
120Ω Twisted Pair
75Ω Coax
120Ω Twisted Pair
11Ω +/- 1%
11Ω +/- 1%
9.5Ω +/- 1%
9.5Ω +/- 1%
560 pF typ.
560 pF typ.
2200 pF typ.
2200 pF typ.
9.31Ω +/- 1%
15Ω +/- 1%
9.31Ω +/- 1%
15Ω +/- 1%
1:2
1:2
1:2
1:2
Table-4 Component Value Differences
5.
Jitter Attenuator 3dB Corner Frequency
The selection of the jitter attenuator’s 3dB corner frequency is different between the LXT385 and the
IDT82V2058. Bit 2 in the Global Control Register (0F Hex) is named JACF bit in LXT385, but the same
bit is named JABW in IDT82V2058. This bit and the depth of the jitter attenuator FIFO will affect the
value of the jitter attenuator 3dB corner frequency in the LXT385. In the IDT82V2058, only the JABW bit
will affect the jitter attenuator 3dB corner frequency. Table 5 describes the details.
LXT385
E1 jitter attenuator 3
dB corner frequency,
host mode
Jitter attenuator 3dB
corner frequency,
hardware mode
32 bit
FIFO
64 bit
FIFO
E1
2.5 Hz
3.5 Hz
3.5 Hz
JACF does
not affect this
figure
JACF and
FIFO do not
affect this
figure
JABW
=0
JABW
=1
E1
IDT82V2058
1.7 Hz
6.5Hz
1.7Hz
FIFO setting does
not affect this
figure
JACF and FIFO
do not affect this
figure
Table 5 – JA 3dB Corner Frequency Selection
6. LPn Setting (loop-back selection pin)
In hardware mode, the status of LPn pin decides the loop back configuration of the corresponding port. For
"No Loop back" setting, the LXT385 and IDT82V2058 are different.
No Loop back on Port
n
LXT385
LPn = Not connected
IDT82V2058
LPn = 0.5 * VDDIO
Table 6 – Loop-back Selection
7. JAS Pin Selection
In hardware mode, the status of the JAS pin (Pin # 87 QFP or Pin #J11 BGA) determines where to put the
Jitter Attenuator. The LXT385 is different from the IDT82V2058 on this point.
JAS(IDT)/JASEL(LXT385)
L
H
High Z
VDDIO/2
JA Position in LXT385 JA Position in IDT82V2058
Transmit Path
Transmit Path
Receive Path
Receive Path
Disabled
Uncertain
Uncertain
Disabled
Table 7 – Jitter Attenuator Selection
8. Default Value of RS register (Reset Register, address is 0A Hex)
Writing to this register will set all registers to their default values. The default value of the RS register in
the LXT385 is "00 Hex". In the IDT82V2058 it is "FF Hex".
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