74AUP1G0832
Low-power 3-input AND-OR gate
Rev. 5 — 22 June 2012
Product data sheet
1. General description
The 74AUP1G0832 provides the Boolean function: Y = (A
×
B) + C. The user can choose
the logic functions OR, AND and AND-OR. All inputs can be connected to V
CC
or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
μA
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G0832GW
−40 °C
to +125
°C
74AUP1G0832GM
74AUP1G0832GF
74AUP1G0832GN
74AUP1G0832GS
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
×
1
×
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
×
1.0
×
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
×
1.0
×
0.35 mm
SOT1115
SOT1202
4. Marking
Table 2.
Marking
Marking code
[1]
aY
aY
aY
aY
aY
Type number
74AUP1G0832GW
74AUP1G0832GM
74AUP1G0832GF
74AUP1G0832GN
74AUP1G0832GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
3
6
4
Y
A
B
C
001aad943
Fig 1. Logic symbol
74AUP1G0832
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 22 June 2012
2 of 19
NXP Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
6. Pinning information
6.1 Pinning
74AUP1G0832
74AUP1G0832
A
GND
1
2
6
5
C
GND
V
CC
B
B
3
001aad940
A
1
6
C
A
GND
74AUP1G0832
1
2
3
6
5
4
C
V
CC
Y
2
5
V
CC
3
4
Y
B
4
Y
001aad941
001aad942
Transparent top view
Transparent top view
Fig 2. Pin configuration SOT363
Fig 3. Pin configuration SOT886
Fig 4.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
A
GND
B
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input A
ground (0 V)
data input B
data output Y
supply voltage
data input C
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
L
H
H
H
H
H
H = HIGH voltage level; L = LOW voltage level.
74AUP1G0832
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 22 June 2012
3 of 19
NXP Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 6
and
7
see
Figure 8
Logic function
2-input AND
2-input OR
3-input gate with the Boolean function: Y = (A
×
B) + C
V
CC
A
B
B
C
Y
A
B
1
2
3
6
5
4
001aad944
Y
B
V
CC
Y
1
2
3
6
5
4
001aad945
C
Y
Fig 5. 2-input AND gate
Fig 6. 2-input OR gate
V
CC
A
C
Y
A
1
2
3
6
5
4
C
Y
A
B
C
V
CC
Y
A
B
1
2
3
6
5
4
C
Y
001aad946
001aad947
Fig 7. 2-input OR gate
Fig 8.
3-input gate with the Boolean function:
Y = (A
×
B) + C
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
−50
[1]
Max
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
output clamping current V
O
< 0 V
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
[2]
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
−50
−65
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
74AUP1G0832
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 22 June 2012
4 of 19
NXP Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
0
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 μA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
μA;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
74AUP1G0832
All information provided in this document is subject to legal disclaimers.
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
×
V
CC
-
0.65
×
V
CC
-
1.6
2.0
-
-
-
-
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.30
×
V
CC
V
0.35
×
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.3
×
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.75
×
V
CC
-
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 22 June 2012
5 of 19
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
