INTEGRATED CIRCUITS
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
Product specification
Supersedes data of 1995 Aug 03
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
FEATURES
•
16-bit transparent latch
•
Multiple V
CC
and GND pins minimize switching noise
•
Power-up 3-State
•
Live insertion/extraction permitted
•
Power-up reset
•
3-State output buffers
•
74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
When nOE is Low, the latched or transparent data appears at the
outputs. When nOE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
Two options are available, 74ABT16373B which does not have the
bus-hold feature and 74ABTH16373B which incorporates the
bus-hold feature.
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1E
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
CC
2D4
2D5
GND
2D6
2D7
2E
•
Output capability: +64mA/–32mA
•
I
CCL
–19 mA maximum
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is High. The latch remains
transparent to the data inputs while nE is High, and stores the data
that is present one setup time before the High-to-Low enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE) controls eight 3-State buffers
independent of the latch operation.
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
SA00379
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
PARAMETER
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Quiescent su ly current
supply
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5V
Outputs low; V
CC
= 5.5V
TYPICAL
2.5
2.0
4
7
500
8
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
48-Pin SSOP type III
48-Pin TSSOP type II
48-Pin SSOP type III
48-Pin TSSOP type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16373B DL
74ABT16373B DGG
74ABTH16373B DL
74ABTH16373B DGG
NORTH AMERICA
BT16373B DL
BT16373B DGG
BH16373B DL
BH16373B DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
1998 Feb 27
2
853-1751 19027
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
PIN DESCRIPTION
PIN NUMBER
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
1, 24
48, 25
4, 10, 15, 21, 28, 34,
39, 45
7, 18, 31, 42
SYMBOL
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
1E, 2E
GND
V
CC
FUNCTION
Data inputs
LOGIC SYMBOL (IEEE/IEC)
1OE
1E
2OE
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
4D
2
∇
1EN
C3
2EN
C4
1
∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Data outputs
Output enable inputs
(active-Low)
Enable inputs
(active-High)
Ground (0V)
Positive supply
voltage
2E
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
3D
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
LOGIC SYMBOL
47
46
44
43
41
40
38
37
2D2
2D3
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1LE
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2D4
2D5
2D6
2D7
SA00380
2
36
3
35
5
33
6
32
8
30
9
29
11
27
12
26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
1998 Feb 27
3
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↓
=
nE
H
H
↓
↓
L
L
H
nDx
L
H
i
h
X
X
Dn
INTERNAL
REGISTER
L
H
L
H
NC
NC
Dn
OUTPUTS
nQ0 – nQ7
L
H
L
H
NC
Z
Z
OPERATING MODE
Enable and read register
Latch and read register
Hold
Disable outputs
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off” state
High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
output in High state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–64
–65 to 150
mA
°C
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
MIN
4.5
0
2.0
0.8
–32
64
10
+85
MAX
5.5
V
CC
UNIT
V
V
V
V
mA
mA
ns/V
°C
1998 Feb 27
4
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B
74ABTH16373B
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
MIN
V
IK
V
OH
V
OL
V
RST
I
I
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
Low-level output voltage
Power-up output voltage
3
Input leakage current
g
74ABT16373B
Input leakage current
74ABTH16373B
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5 5V; V
I
= V
CC
or GND
5.5V;
V
CC
= 5.5V; V
I
= V
CC
or GND
I
I
V
CC
= 5.5V; V
I
= V
CC
V
CC
= 5.5V; V
I
= 0
V
CC
= 4.5V; V
I
= 0.8V
I
HOLD
Bus Hold current A inputs
6
74ABTH16373B
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output current
1
Output High leakage
current
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
I
OFF
I
PU
/I
PD
I
OZH
I
OZL
I
O
I
CEX
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current
per input pin
2
74ABT16373B
Additional supply current
per input pin
2
74ABTH16373B
Quiescent supply current
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.1V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= GND
V
CC
= 5.5V; V
O
= 5.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.0V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V, other inputs
at V
CC
or GND
V
CC
= 5.5V; one input at 3.4V, other inputs
at V
CC
or GND
–50
Control pins
Data pins
5
50
–75
±800
±5.0
±5.0
0.5
–0.5
–70
0.1
0.5
8
0.5
±100
±50
10
–10
–180
50
2
19
2
–50
±100
±50
10
–10
–180
50
2
19
2
µA
µA
µA
µA
mA
µA
mA
mA
mA
µA
2.5
3.0
2.0
TYP
–0.9
2.9
3.4
2.4
0.42
0.13
±0
01
±0.01
±0.01
0.01
–1
0.55
0.55
±1
±1
1
–3
50
–75
µA
MAX
–1.2
2.5
3.0
2.0
0.55
0.55
±1
±1
1
–5
T
amb
= –40°C
to +85°C
MIN
MAX
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
UNIT
5
100
100
∆I
CC
0.5
1.5
1.5
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V, with a transition time of up to 10msec. From V
CC
= 2.1 to V
CC
= 5V
±
10% a
transition time of up to 100µsec is permitted.
5. Unused pins at V
CC
or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
5
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