Table 1. SRAM Device Control Operation Truth Table
G
X
X
L
X
W
X
X
H
L
X
E2
X
L
H
H
X
E1
H
X
L
L
L
I/O Mode
DQ(31:0)
3-State
DQ(31:0)
3-State
DQ(31:0)
Data Out
DQ(31:0)
Data In
DQ(31:0)
All 3-State
Mode
Standby
Standby
Word Read
Word Write
3-State
V
DD1
A11
A12
A13
A14
A15
A16
E1
G
E2
V
DD2
V
SS
Figure 2. 20ns SRAM Pinout (68)
Note:
Pin 30 on the UT8ER512K32S (Slave) is a no connect (NC).
PIN DESCRIPTIONS
Pins
A(18:0)
DQ(31:0)
E1
E2
W
G
V
DD1
V
DD2
V
SS
MBE
SCRUB
SCRUB
BUSY
BUSY
Type
I
BI
I
I
I
I
P
P
P
TTO
I
O
NC
O
Description
Address
Data Input/Output
Enable (Active Low)
Enable (Active High)
Write Enable
Output Enable
Power (1.8)
Power (3.3V)
Ground
Multiple Bit Error
Slave SCRUB Input
Master SCRUB Output
Slave No Connect
Master Wait State Control
Busy
MBE
V
DD2
V
SS
H
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
Table 2. EDAC Control Pin Operation Truth Table
MBE
H
L
X
X
SCRUB
H
H
H
H
BUSY
H
H
H
L
I/O Mode
Read
Read
X
X
Mode
Uncorrectable Bit
Error
Valid Data Out
Device Ready
Device Ready / Early
Scrub Request
Coming
Device Busy
X
L
X
Not
Accessible
Notes:
1. “X” is defined as a “don’t care” condition
3
READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1 and
G less than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(31:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as device
enable and output enable are active, the minimum time between
valid address changes is specified by the read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by the latter of either E1and E2 going
active while G remains asserted, W remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t
ETQV
is satisfied, the 32-bit word addressed by A(18:0) is
accessed and appears at the data outputs DQ(31:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is t
GLQV
unless t
AVQV
or t
ETQV
(reference Figure
3b) have not been satisfied.
SRAM EDAC Status Indications during a Read Cycle, if MBE
is Low, the data is good. If MBE is High the data is corrupted.
WRITE CYCLE
A combination of W and E1 less than V
IL
(max) and E2 greater
than V
IH
(min) defines a write cycle. The state of G is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either G is greater than V
IH
(min), or when
W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure 4a,
is defined by a write terminated by W going high, with E1 and
E2 still active. The write pulse width is defined by t
WLWH
when
the write is initiated by W, and by t
ETWH
when the write is
initiated by E1 and E2. Unless the outputs have been previously
placed in the high-impedance state by G, the t
WLQZ
before
applying data to the 32 bidirectional pins DQ(31:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure 4b,
is defined by a write terminated by the latter of E1 or E2 going
inactive. The write pulse width is defined by t
WLEF
when the
write is initiated by W, and by t
ETEF
when the write is initiated
by either E1or E2 going active. For the W initiated write, unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait t
WLQZ
before applying data to the
thirty-two bidirectional pins DQ(31:0) to avoid bus contention.
MEMORY SCRUBBING/CYCLE STEALING
The UT8ER512K32 SRAM uses architectural improvements
and embedded error detection and correction to maintain
unsurpassed levels of SEU protection. This is accomplished by
what Aeroflex refers to as Cycle Stealing. To minimize the
system design impact for reduced speed operation, the edge
relationship between BUSY and SCRUB is programmable via
the sequence described in figure 5a.
The effective error rate will be flux dependent (rate at which
radiation is applied) and not simply LET dependent. As a result,
some users may desire an increased scrub rate to lower the error
rate at the sacrifice of reduced total throughput, while others
may desire a lower scrub rate to increase the total throughput
and accept a higher error rate in a low flux environment. This
rate at which the SRAM controller will correct errors from the
memory is user programmable. The required sequence is
described in figure 5a.
Data is corrected not only during the internal scrub, but again
during a user requested read cycle. The MBE signal is asserted
once the data is valid (t
AVAV
), if the data presented contains at
least two errors and should be considered corrupt. (Note:
Reading un-initialized memory locations may result in un-
intended MBE assertions.)
RADIATION HARDNESS
The UT8ER512K32 SRAM incorporates special design, layout,
and process features which allows operation in a limited
radiation environment.
Table 3. Radiation Hardness Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
100K
TBD
rad(Si)
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles >100MeV-cm
2
/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
SUPPLY SEQUENCING
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
4
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage (Core)
DC supply voltage (I/O)
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 2.0V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
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