IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
IDT74ALVC16835
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVC16835:
– High Output Drivers: ±24mA
– Suitable for heavy loads
–
–
–
DESCRIPTION:
This 18-bit universal bus driver is built using advanced dual metal
CMOS technology. Data flow from A to Y is controlled by the output-
enable (OE) input. The device operates in the transparent mode when
the latch-enable (LE) input is high. The A data is latched if the clock (CLK)
input is held at a high or low logic level. If LE is low, the A data is stored
in the latch flip-flop on the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
The ALVC16835 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
•
SDRAM Modules
•
PC Motherboards
•
Workstations
Functional Block Diagram
OE
27
CLK
30
LE
28
A
1
54
1
D
3
C
1
CLK
Y
1
TO 17 OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4478/-
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
NC
Y
1
G ND
Y
2
Y
3
V
CC
Y
4
Y
5
Y
6
G ND
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
G ND
Y
13
Y
14
Y
15
V
CC
Y
16
Y
17
G ND
Y
18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G ND
NC
A
1
G ND
A
2
A
3
V
CC
A
4
A
5
A
6
G ND
A
7
A
8
A
9
A
10
A
11
A
12
G ND
A
13
A
14
A
15
V
CC
A
16
A
17
G ND
A
18
CLK
G ND
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
(1)
Inputs
OE
H
LE
X
H
H
L
L
L
L
CLK
X
X
X
↑
↑
H
L
Ax
X
L
H
L
H
X
X
Outputs
Yx
Z
L
H
L
H
Y
0(2)
Y
0(3)
SSOP/
TSSOP/ TVSOP
TOP VIEW
L
L
L
L
L
PIN DESCRIPTION
Pin Names
OE
CLK
LE
Ax
Yx
NC
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Latch Enable (Transparent HIGH)
Data Inputs
3-State Outputs
No Internal Connection
c 1998 Integrated Device Technology, Inc.
L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. Output level before indicated steady-state input conditions were estab-
lished, provided that CLK is HIGH before LE went HIGH.
3. Output level before the indicated steady-state input conditions were es-
tablished.
2
DSC-123456
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
3
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
26
12
V
CC
= 3.3V ± 0.3V
Typical
31
14
Unit
pF
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
H
t
H
t
SK
(o)
Parameter
Propagation Delay
Ax to Yx
Propagation Delay
LE to Yx
Propagation Delay
CLK to Yx
Output Enable Time
OE
to Yx
Output Disable Time
OE
to Yx
Pulse Duration, LE HIGH
Pulse Duration, CLK HIGH or LOW
Setup Time, data before CLK↑
Setup Time, data before LE↓, CLK HIGH
Setup Time, data before LE↓, CLK LOW
Hold Time, data after CLK↑
Hold Time, data after LE↓,
CLK HIGH or LOW
Output Skew
(2)
Min
.
150
1
1.3
1.4
1.4
1
3.3
3.3
2.2
1.9
1.3
0.6
1.4
—
Max.
—
4.2
5
5.5
5.5
4.5
—
—
—
—
—
—
—
—
V
CC
= 2.7V
Min
.
150
—
—
—
—
—
3.3
3.3
2.1
1.6
1.1
0.6
1.7
—
Max.
—
4.2
4.9
5.2
5.6
4.3
—
—
—
—
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min
.
150
1
1.3
1.4
1.1
1.3
3.3
3.3
1.7
1.5
1
0.7
1.4
—
Max.
—
3.6
4.2
4.5
4.6
3.9
—
—
—
—
—
—
—
500
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS FROM 0
0
C TO 65
0
C, C
L
=50 pF
V
CC
= 3.3V ± 0.15V
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
CLK to Yx
Min.
1.7
Max.
4.5
Unit
ns
4
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
NEW16link
SAM E PHAS E
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORM ALLY
CLOSE D
LOW
t
PZH
OUTPUT
SW ITCH
NORM ALLY
OPEN
HIGH
V
LOAD /2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD /2
V
LZ
V
OL
V
OH
V
HZ
0V
V
LOAD
Open
GND
V
IN
D.U.T.
V
OU T
R
T
500
Ω
C
L
ALV C Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALV C Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
NEW16link
t
R EM
GND
Open
t
S U
t
H
OUTPUT SKEW -
INPUT
TSK
(x)
t
PH L1
V
IH
V
T
0V
V
OH
t
PLH1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALV C Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
P HL1
ALV C Link
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
