ADVANCE INFORMATION
GALVANTECH
, INC.
SYNCHRONOUS
DUAL-PORT
BURST SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
True Dual-Ported memory cells which allow simultaneous
access of the same memory location.
Fast access times: 4.5ns, 5.0ns, and 6.0ns
Fast clock speed: 125, 100, 83, and 66MHz
Fast OE# access times: 4.5ns, 5.0ns, and 6.0ns
Address, data and control registers
5.0V + 0.5V power supply
Address burst counters enable and reset capabilities
Dual Chip Enables for easy depth expansion
Fully synchronous interface on both ports
3 operating modes: Flow-Through, Pipelined, and Burst
Dual chip enables for depth expansion
BYTE ENABLE controls for x16 and x18 devices
Internally self-timed WRITE CYCLE
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP package
Clock Cycle Timing
8ns (125MHz)
10ns (100MHz)
12ns (83MHz)
15ns (67MHz)
16K x 16
16K x 18
32K x 16
32K x 18
64K x 16
64K x 18
32K x 8
32K x 9
64K x 8
64K x 9
128K x 8
128K x 9
GVT7464/32/16C16/18
GVT74128/64/32C8/9
64K/32K/16K x 16/18
128K/64K/32K x 8/9
+5V SUPPLY, BURST COUNTER
GNERAL DESCRIPTION
The
GVT7416C16/18,
GVT7432C16/18,
and
GVT7464C16/18 are high speed synchronous 16K, 32K and
64K x 16/18 dual-port static RAMs; the GVT7432C8/9,
GVT7464C8/9, and GVT74128C8/9 are high speed
synchronous 32K, 64K, and 128K x 8/9 dual-port static
RAMs. Dual-port memory cells are provided, permitting
independent, simultaneous access for reads and writes to any
address location in these devices. Registers on address, data,
and control inputs allow for minimal set-up and hold times.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK).
Each port contains a burst counter on the input address
register for internal burst operation. The address burst counter
can be incremented, suspended or reset to zero, depending
upon the CNTEN# and CNTRST# pins.
In the pipelined mode, output data will be valid after one
cycle delay. Flow-through mode can be used to bypass the
pipelined output register to eliminate one cycle latency.
Pipelined or flow-through mode is selected by the FT# pin.
The port of the device is activated by asserting LOW on
CE0# and HIGH on CE1 at the rising edge of CLK. By
asserting HIGH on CE0# or LOW on CE1 at the rising edge
of CLK signal will power down the internal circuitry to
reduce the static power consumption. The use of multiple
Chip Enables allows easier banking of multiple chips for
depth expansion configurations.
Counter enable inputs are provided to utilize the internal
address generated by the internal counter for fast memory
applications. A port’s address burst conter is loaded with the
port’s address strobe (ADS#). When the port’s count enable
(CNTEN#) is asserted, the address burst counter will
increment on each LOW-to-HIGH transition of the port’s
clock signal. This will read/write one word from/into each
successive address location until CNTEN is deasserted. The
address burst counter can address the entire memory array and
will loop back to the start. Counter reset (CNTRST#) is used
to reset the address burst counter.
MARKING
-8
-10
-12
-15
GVT7416C16
GVT7416C18
GVT7432C16
GVT7432C18
GVT7464C16
GVT7464C18
GVT7432C8
GVT7432C9
GVT7464C8
GVT7464C9
GVT74128C8
GVT74128C9
T
Configurations
Package Versions
100-pin TQFP
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 8/99
Galvantech, Inc. reserves the right to change
products or specifications without notice.
LED专区
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
