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74LVC125A-Q100
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 1 — 4 April 2013
Product data sheet
1. General description
The 74LVC125A-Q100 consists of four non-inverting buffers/line drivers with 3-state
outputs (nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes
the outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74LVC125A-Q100
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC125AD-Q100
40 C
to +125
C
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads; body
width 3.9 mm; body thickness 1.47 mm
Version
SOT108-1
Type number
74LVC125APW-Q100
40 C
to +125
C
74LVC125ABQ-Q100
40 C
to +125
C
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
14 terminals; body 2.5
3
0.85 mm
SOT762-1
4. Functional diagram
2
1
5
4
9
10
12
13
1A
1OE
2A
2OE
1Y
3
2
1
3
2Y
6
1
5
EN1
6
4
3A
3OE
4A
4OE
mna228
3Y
8
9
8
10
4Y
11
12
11
13
nA
nY
nOE
mna229
mna227
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74LVC125A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
2 of 15
NXP Semiconductors
74LVC125A-Q100
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
5. Pinning information
5.1 Pinning
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/9&$4
2(
*1'
<
*1'
WHUPLQDO
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$
<
2(
$
<
9
&&
2(
$
<
2(
$
9
&&
2(
$
<
2(
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<
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 4.
Pin configuration for SO14 and TSSOP14
Fig 5.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
data enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
1OE, 2OE, 3OE, 4OE 1, 4, 10, 13
6. Functional description
Table 3.
Inputs
nOE
L
L
H
[1]
Function selection
[1]
Output
nA
L
H
X
nY
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
74LVC125A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
3 of 15
NXP Semiconductors
74LVC125A-Q100
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
500
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW-state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
C
derate linearly with 8 mW/K.
For TSSOP14 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
output HIGH or LOW state
output 3-state
Conditions
Min
1.65
1.2
0
0
0
40
0
0
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
74LVC125A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
4 of 15
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