NB2304A
3.3V Zero Delay
Clock Buffer
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks in PC, workstation, datacom, telecom
and other high−performance applications. It is available in an 8 pin
package. The part has an on−chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
input−to−output propagation delay is guaranteed to be less than
250 ps, and the output−to−output skew is guaranteed to be less than
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304Ax1H is the high−drive version of
the
−1
and the rise and fall times on this device are much faster.
The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X
frequencies on each output Bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
The NB2304Ax5H is a high−drive version with REF/2 on both
Banks.
Features
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MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
XXXX
ALYW
XXXX
ALYW
XXXX
A
L
Y
W
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
•
Zero Input
−
Output Propagation Delay, Adjustable by Capacitive
•
•
•
•
•
•
•
•
•
•
•
•
Load on FBK Input
Multiple Configurations
−
Refer to NB2304A Configurations Table
Input Frequency Range: 10 MHz to 133 MHz
Multiple Low−Skew Outputs
Output−Output Skew < 200 ps
Device−Device Skew < 500 ps
Two Banks of Four Outputs
Less than 200 ps Cycle−to−Cycle Jitter (−1,
−1H, −5H)
Available in Space Saving, 8 pin 150 mil SOIC Packages and
Standard TSSOP
3.3 V Operation
Advanced 0.35
m
CMOS Technology
Industrial Temperature Available
Pb−Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
©
Semiconductor Components Industries, LLC, 2005
February, 2005
−
Rev. 0
1
Publication Order Number:
NB2304A/D
NB2304A
FBK
CLKA1
REF
PLL
CLKA2
B2
Extra Divider (−2)
CLKB1
CLKB2
Figure 1. Basic Block Diagram
(see Figures 11, 12 and 13 for device specific Block Diagrams)
Table 1. CONFIGURATIONS
(x = C for Commercial; I for Industrial)
Device
NB2304Ax1
NB2304Ax1H
NB2304Ax2
NB2304Ax2
NB2304Ax5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
Reference
B2
Reference
Reference
Reference
B2
Reference
Reference
B2
Bank B Frequency
Table 2. PIN DESCRIPTION
Pin #
REF
CLKA1
CLKA2
GND
1
2
8
7
FBK
V
DD
CLKB2
CLKB1
1
2
3
6
5
4
5
4
6
7
Pin Name
REF (Note 1)
CLKA1 (Note 2)
CLKA2 (Note 2)
GND
CLKB1 (Note 2)
CLKB2 (Note 2)
V
DD
FBK
Description
Input reference frequency, 5 V toler-
ant input.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
Ground.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
3.3 V supply.
PLL feedback input.
NB2304A
3
Figure 2. Pin Configuration
8
1. Weak pulldown.
2. Weak pulldown on all outputs.
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2
NB2304A
Table 3. MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Maximum Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (per MIL−STD−883, Method 3015)
Min
−0.5
−0.5
−0.5
−65
Max
+7.0
V
DD
+ 0.5
7
+150
260
150
> 2000
Unit
V
V
V
°C
°C
°C
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 4. OPERATING CONDITIONS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance (Note 3)
Description
Min
3.0
0
Max
3.6
70
30
15
7
Unit
V
°C
pF
pF
pF
3. Applies to both REF Clock and FBK.
Table 5. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (−1,
−2)
I
OL
= 12 mA (−1H,
−5H)
I
OH
=
−8
mA (−1,
−2)
I
OH
=
−12
mA (−1H,
−5H)
Unloaded outputs 100 MHz REF
Select inputs at V
DD
or GND
Unloaded outputs, 66 MHz REF (−1,
−2)
Unloaded outputs, 33 MHz REF (−1,
−2)
2.4
TBD
TBD
TBD
TBD
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
mA
mA
V
V
mA
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3
NB2304A
Table 6. SWITCHING CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
t
1
Description
Output Frequency
Test Conditions
30 pF load (all devices)
20 pF load (−1H,
−5H)
p
(
,
)
15 pF load (−1,
−2)
Measured at 1.4 V, F
OUT
= 66.66 MHz
30 pF load
Measured at 1.4 V, F
OUT
v
50 MHz
15 pF load
t
3
Output Rise Time
( , )
(−1,
−2)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Output Rise Time
(−1H,
−5H)
t
4
Output Fall Time
( , )
(−1,
−2)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 2.0 V and 0.8 V
30 pF load
Measured between 2.0 V and 0.8 V
15 pF load
Output Fall Time
(−1H,
−5H)
t
5
Output−to−Output Skew on same Bank
(−1,
−2)
Output−to−Output Skew
(−1H,
−5H)
Output Bank A−to−Output Bank B Skew
(−1,
−5H)
Output Bank A−to−Output Bank B Skew
(−2)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to FBK Rising
Edge
Device−to−Device Skew
Output Slew Rate
Cycle−to−Cycle Jitter
( ,
−1H, −5H)
(−1,
,
)
Measured between 2.0 V and 0.8 V
30 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of the
device
Measured between 0.8 V and 2.0 V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
Cycle−to−Cycle Jitter
( )
(−2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF and FBK pins
1
175
200
100
400
375
1.0
ms
ps
0
0
Min
10
Typ
Max
100
133.3
133.3
50.0
50.0
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
200
200
400
±250
500
ps
ps
V/ns
ps
ps
ns
ns
Unit
MHz
t
1
Duty Cycle = (t
2
/ t
1
) * 100
(all devices)
(
)
40.0
45.0
%
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4
NB2304A
Table 7. OPERATING CONDITIONS FOR INDUSTRIAL TEMPERATURE DEVICES
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance (Note 4)
Description
Min
3.0
−40
Max
3.6
85
30
15
7
Unit
V
°C
pF
pF
pF
4. Applies to both REF Clock and FBK.
Table 8. ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL TEMPERATURE DEVICES
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (−1,
−2)
I
OL
= 12 mA (−1H,
−5H)
I
OH
=
−8
mA (−1,
−2)
I
OH
=
−12
mA (−1H,
−5H)
Unloaded outputs 100 MHz REF
Select inputs at V
DD
or GND
Unloaded outputs, 66 MHz REF
(−1,
−2)
Unloaded outputs, 33 MHz REF
(−1,
−2)
2.4
TBD
TBD
TBD
TBD
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
mA
mA
V
V
mA
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5
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