SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
D
D
D
D
Organization . . . 262 144 Words
×
4 Bits
Single 5-V Supply (10% Tolerance)
Processed to MIL-STD-833, Class B
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
ta(R)
ta(C)
ta(CA) WRITE
(tRAC)
(tCAC)
(tCAA) CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
190 ns
120 ns
30 ns
55 ns
220 ns
150 ns
40 ns
70 ns
260 ns
D
D
D
3-State Unlatched Output
Low Power Dissipation
Packaging Offered:
– 20-Pin 300-Mil Ceramic DIP (JD Suffix)
– 20-Lead Ceramic Surface-Mount Package
(HJ Suffix)
– 20-Pin Ceramic Flat Pack (HK Suffix)
– 20-Terminal Leadless Ceramic
Surface-Mount Package (FQ Suffix)
– 20-Terminal Low-Profile Leadless
Ceramic Surface-Mount Package
(HL Suffix)
– 20-Pin Ceramic Zig Zag In-Line Package
(SV Suffix)
Operating Free-Air Temperature Range
– 55°C to 125°C
D
D
D
SMJ44C256-80
SMJ44C256-10
SMJ44C256-12
SMJ44C256-15
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
Long Refresh Period
512-Cycle Refresh in 8 ms (Max)
All Inputs and Clocks are TTL Compatible
D
JD PACKAGE
( TOP VIEW )
HJ PACKAGE
( TOP VIEW )
PIN NOMENCLATURE
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
V
CC
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
V
SS
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
A0 – A8
CAS
DQ1 – DQ4
G
RAS
TF
VCC
VSS
W
Address Inputs
Column Address Strobe
Data In / Data Out
Data Output Enable
Row Address Strobe
Test Function
5-V Supply
Ground
Write Enable
FQ / HL PACKAGES
( TOP VIEW )
SV PACKAGE
( TOP VIEW )
HK PACKAGE
( TOP VIEW )
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
V
CC
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
V
SS
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
G
DQ3
V
SS
DQ2
RAS
A0
A2
V
CC
A5
A7
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
CAS
DQ4
DQ1
W
TF
A1
A3
A4
A6
A8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1995, Texas Instruments Incorporated
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1
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
description
The SMJ44C256 series is a set of high-speed, 1 048 576-bit dynamic random access memories (DRAMs),
organized as 262 144 words of four bits each. These devices employ technology for high performance,
reliability, and low power.
These devices feature maximum RAS access times of 80 ns, 100 ns,120 ns, and 150 ns. Maximum power
dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.
I
CC
peaks are 140 mA typical, and an input voltage undershoot of –1 V can be tolerated, minimizing system noise
considerations.
All inputs and outputs, including clocks, are compatible with Series 54 /174 TTL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ44C256 is offered in 20-pin ceramic dual-in-line packages (JD suffix) and 20/26-terminal ceramic
leadless carriers (FQ / HL suffixes), 20/26-pin leaded carrier (HJ suffix), a 20-pin flatpack (HK suffix), and a
20-pin ceramic zig-zag in-line package (SV suffix). They are specified for operation from –55°C to125°C.
logic symbol
†
A0
A1
A2
A3
A4
A5
A6
A7
A8
6
7
8
9
11
12
13
14
15
20D17/21D8
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21/[COLUMN]
G24
CAS
W
G
17
3
16
&
23,21D
G25
23C22
24,25EN
A
0
262 143
RAM 256K
×
4
20D9/21D0
RAS
4
DQ1
DQ2
DQ3
DQ4
1
2
18
19
A,22D
∇
26
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the JD package.
2
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HOUSTON, TEXAS 77251–1443
SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
functional block diagram
RAS
CAS
W
G
Timing and Control
Row
Address
Buffers
(9)
256K
Array
A0
A1
A2
A3
A4
A5
A6
A7
A8
Row
Decode
256K
Array
Sense Amplifiers
Column
Address
Buffers
(9)
Data
In
Reg
4
Column Decode
I/O
Buffers
4 of 8
Selection
Data
Out
Reg
4
4
Sense Amplifiers
256K
Array
Row
Decode
256K
Array
DQ1–DQ4
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the CAS page cycle
time used. With minimum CAS page cycle time, all 512 columns specified by column addresses A0 through A8
can be accessed without intervening RAS cycles.
Unlike conventional page mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The column address
latches to the first CAS falling edge. This feature allows the SMJ44C256 to operate at a wider data bandwidth
than conventional page mode parts, since data retrieval begins as soon as column address is valid rather than
when CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column
address can be presented immediately after t
h(RA)
(row address hold time) has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after t
a(C)
maximum (access time from CAS
low), if t
a(CA)
maximum (access time from column address) has been satisfied. In the event that column
addresses for the next page cycle are valid at the time CAS goes high, access time for the next cycle is
determined by the later occurrence of t
a(C)
or t
a(CP)
(access time from rising edge of CAS).
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SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
address (A0 through A8)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set
up on pins A0 through A8 and latched onto the chip by RAS. Nine column-address bits are set up on pins A0
through A8 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
In the SMJ44C256, CAS is used as a chip select, activating the output buffer as well as latching the address
bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without a
pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS
(early-write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
G grounded.
data in (DQ1–DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, the data is strobed in by W with setup and hold times referenced
to this signal. In a delayed-write or read-modify-write cycle, G must be high to bring the output buffers to the
high-impedance state prior to applying data to the I/O lines.
data out (DQ1–DQ4)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and G are brought low. In a read cycle the output becomes valid after the access time interval t
a(C)
that begins with the negative transition of CAS as long as t
a(R)
and t
a(CA)
are satisfied. The output becomes valid
after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns it
to a high-impedance state. This is accomplished by bringing G high prior to applying data, thus satisfying t
d(GHD)
.
output enable (G)
G controls the impedance of the output buffers. When G is high, the buffers remain in the high-impedance state.
Bringing G low during a normal cycle activates the output buffers, putting them in the low-impedance state. It
is necessary for both G and CAS to be brought low for the output buffers, to go into the low-impedance state.
Once in the low-impedance state, they remain in the low-impedance state until either G or CAS is brought high.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (A0 – A8). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle.
CBR refresh
CBR refresh is utilized by bringing CAS low earlier than RAS [see parameter t
d(CLRL)R
] and holding it low after
RAS falls [see parameter t
d(RLCH)R
]. For successive CBR refresh cycles, CAS can remain low while cycling
RAS. The external address is ignored and the refresh address is generated internally. The external address is
also ignored during the hidden refresh option.
4
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SMJ44C256
262144 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
power up
To achieve proper device operation, an initial pause of 200
µs
followed by a minimum of eight initialization
(refresh) cycles is required after power-up to the full V
CC
level.
test function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal
to V
CC
.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
VCC
VSS
VIH
VIL
TA
Supply voltage
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
–1
– 55
4.5
NOM
5
0
6.5
0.8
MAX
5.5
UNIT
V
V
V
V
°
C
TC
Case temperature
125
°
C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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