DATASHEET
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
Description
The ICS527-01 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. A SYNC
pulse indicates when the rising clock edges are aligned
with zero skew. Using Phase-Locked Loop (PLL)
techniques, the device accepts an input clock up to 200
MHz and produces an output clock up to 160 MHz.
The ICS527-01 aligns rising edges on ICLK and FBIN
at a ratio determined by the reference and feedback
dividers.
For configurable clocks that do not require zero delay,
use the ICS525.
ICS527-01
Features
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Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
Pin configurable multiplication/division ratio
Slices frequency or period
SYNC pulse output indicates aligned edges
Input clock frequency of 600 kHz to 200 MHz
Output clock frequencies up to 160 MHz
Very low jitter
Duty cycle of 45/55 up to 160 MHz
Operating voltage of 3.3V
Pin selectable drive strength
Multiple outputs available when combined with
fanout buffers
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Industrial temperature version available
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Available in Pb (lead) free package
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
R6:R0
7
Reference
Divider
Feedback
Divider
PDTS
CLK1
PLL
Divide
by 2
PDTS
1
0
CLK2
Feedback can
come from
CLK1 or CLK2
(not both)
S1:S0
2
GND
2
VDD
2
2xDRIVE
ICLK
FBIN
SYNC
PDTS
OECLK2
7
F6:F0
DIV2
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 1
ICS527-01
REV F 092209
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
R5
R6
DIV2
S0
S1
VDD
ICLK
FBIN
GND
OECLK2
2XDRIVE
F0
F1
F2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
F6
F5
F4
F3
Frequency Range Table
S1 S0
0
0
1
1
0
1
0
1
CLK1 Output Frequency (MHz)
Commercial (0 to 70°C)
37 - 75
18 - 37
4 - 10
75 -160
Industrial (-40 to 85°C)
35 - 70
16 - 35
4-8
70 - 140
To cover the range from 10 to 18 MHz (0 to 70°C) and 8
to 16 MHz (-40 to 85°C), select address 01 to generate
2x your desired output frequency, then configure CLK2
to generate CLK1/2.
CLK2 Operation Table
OECLK2
0
1
1
DIV2
X
0
1
CLK2
Z
SYNC
CLK1/2
CLK Drive Select Table
2XDRIVE
0
1
Output Drive
12 mA
25 mA
28 pin 150 mil body SSOP
Pin Descriptions
Pin
Number
1,2, 24-28
3
4, 5
6, 23
7
8
9, 20
10
11
12-18
19
21
22
Pin
Name
R5, R6,
R0-R4
DIV2
S0, S1
VDD
ICLK
FBIN
GND
OECLK2
2XDRIVE
F0-F6
PDTS
CLK2
CLK1
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up resistor.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up resistor.
Select pins for output divider determined by user. See table above. Internal
pull-up resistor.
Connect to VDD.
Reference clock input.
Feedback clock input.
Connect to ground.
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up resistor.
Clock output drive strength doubled when high. Internal pull-up resistor.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up resistor.
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up resistor.
Output clock 2. Can be SYNC output or a low skew divide by 2 of CLK1.
Output clock 1.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 2
ICS527-01
REV F 092209
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS527-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. The
capacitor must be connected close to the device to
minimize lead inductance.
ICLK
CLK1
CLK2
phase is
indeterminate
CLK1 Feedback
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
ICLK
CLK1
CLK2
CLK2 Feedback
Using the Clock Slicer
First use DIV2 to select the function of the CLK2 output.
If DIV2 is high, a divide-by-2, low skew version of CLK1
is present on CLK2. If DIV2 is low, a SYNC pulse is
generated on CLK2. The SYNC pulse goes high
synchronously with the rising edges of ICLK and CLK1
that are de-skewed. The SYNC function operates at
CLK1 frequencies up to 66 MHz. If neither CLK1/2 or a
SYNC pulse are required, then CLK2 should be
disabled by connecting OECLK2 to ground. This will
also give the lowest jitter on CLK1.
Next, the feedback scheme should be chosen. If CLK2
is being used as a SYNC pulse, or is tri-stated, then
CLK1 must be connected to FBIN. If CLK2 is selected
to be CLK1/2 (DIV2=1, OECLK2=1) then either CLK1 or
CLK2 must be connected to FBIN. The choice between
CLK1 or CLK2 is illustrated by the following examples
where the device has been configured to generate
CLK1 that is twice the frequency on ICLK.
Using CLK1 as feedback will always result in
synchronized rising edges between ICLK and CLK1 if
CLK1 is used as feedback. CLK2 could be a falling edge
compared to ICLK. Therefore, wherever possible, it is
recommended to use CLK2 for feedback, which will
synchronize the rising edges of all three clocks.
More complicated feedback schemes can be used,
such as incorporating multiple output buffers in the
feedback path. An example is given later in the
datasheet. The fundamental property of the ICS527-01
is that it aligns rising edges on ICLK and FBIN at a ratio
determined by the reference and feedback dividers.
The drive strength is selected by the 2XDRIVE pin. If
high drive strength is required, we recommend tying this
pin low.
Lastly, the divider settings should be selected. This is
described in the following section.
Determining ICS527-01 Divider Settings
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins directly
to ground (or VDD, although this is not required
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 3
ICS527-01
REV F 092209
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-01 automatically produces
the correct clock when all components are soldered. It
is also possible to connect the inputs to parallel I/O
ports in order to switch frequencies.
The output of the ICS527-01 can be determined by the
following simple equation:
S1 and S0 should be set for the frequency of CLK1,
according to the Frequency Range Table on page 2.
The device can be operated below the lower limits
stated in table 2, however, jitter and skew may be
higher. Therefore, if your expected output frequency
covers more than one frequency range, use the
setting for the highest frequency expected.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3 which
gives the required 5/4 multiplication. Then R6:R0 is
0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this
example assumes CLK1 is connected to FBIN.S1:S0 is
set by referring to the Frequency Range Table. The
setting for 50 MHz is 00.
For assistance with configuring the device, please send
a description of your requirements using the “Technical
Support” link at www.icst.com.
FDW + 2
-
FB Frequency
= Input Frequency
×
-----------------------
RDW + 2
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Also, the following operating ranges should be
observed:
Input Frequency
-
300kHz
<
------------------------------------------
RDW + 2
Typical Example
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 4
ICS527-01
REV F 092209
ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the 1x
output drive is selected.T
VDD
R5
R6
DIV2
S0
0.01 F
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
F6
F5
F4
F3
33
0.01 F
S1
VDD
40 MHz
ICLK
FBIN
GND
OECLK2
2XDRIVE
F0
F1
F2
50 MHz
SYNC
33
Note: The series termination resistor is located before the feedback trace.
This will give the following waveforms:
40 MHz
ICLK
50 MHz
CLK1
SYNC
CLK2
Multiple Output Example
In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies
of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the
MK74CB218 which has dual 1 to 8 buffers with low pin-to-pin skew.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 5
ICS527-01
REV F 092209
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